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SMAS Memory Map

Displaying 20 out of 1220 addresses.

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Regs Address Length Type Description Details
$4351 1 byte SNES Register (DMA) rwb++++ BBAD5 - DMA Destination Register for Channel 5 pppppppp This specifies the Bus B address to access. Considering the standard CPU memory space, this specifies which address $00:2100-$00:21FF to access, with two- and four-register modes wrapping $21FF->$2100, not $2200. The effect of writing this register during HDMA to the associated channel is unknown. Most likely, the change takes effect for the next transfer. This register is set to $FF on power on, and is unchanged on reset.
$4352 3 bytes SNES Register (DMA) rwl++++ A1T5L - DMA Source Address for Channel 5 low byte rwh++++ A1T5H - DMA Source Address for Channel 5 high byte rwb++++ A1B5 - DMA Source Address for Channel 5 bank byte bbbbbbbb hhhhhhhh llllllll This specifies the starting Address Bus A address for the DMA transfer, or the beginning of the HDMA table for HDMA transfers. Note that Bus A does not access the Bus B registers, so pointing this address at say $00:2100 results in open bus. The effect of writing this register during HDMA to the associated channel is unknown. However, current theory is that only $4354 will affect the transfer. The changes will take effect at the next HDMA init. During DMA, $4352/3 will be incremented or decremented as specified by $4352/3. However $4354 will NOT be adjusted. These registers will not be affected by HDMA. This register is set to $FF on power on, and is unchanged on reset.
$4355 3 bytes SNES Register (DMA) rwl++++ DAS5L - DMA Size/HDMA Indirect Address low byte rwh++++ DAS5H - DMA Size/HDMA Indirect Address high byte rwb++++ DASB5 - HDMA Indirect Address bank byte bbbbbbbb hhhhhhhh llllllll For DMA, $4355/6 indicate the number of bytes to transfer. Note that this is a strict limit: if this is set to 1 then only 1 byte will be written, even if the transfer mode specifies 2 or 4 registers (and if this is 5, all 4 registers would be written once, then the first only would be written a second time). Note, however, that writing $0000 to this register actually results in a transfer of $10000 bytes, not 0. $4355/6 are decremented during DMA, and thus typically end up set to 0 when DMA is complete. For HDMA, $4357 specifies the bank for indirect addressing mode. The indirect address is copied into $4355/6 and incremented appropriately. For direct HDMA, these registers are not used or altered. Writes to $4357 during indirect HDMA will take effect for the next transfer. Writes to $4355/6 during indirect HDMA will also take effect for the next HDMA transfer, however this is only noticable during repeat mode (for normal mode, a new indirect address will be read from the table before the transfer). For a direct transfer, presumably nothing will happen. This register is set to $FF on power on, and is unchanged on reset.
$4358 2 bytes SNES Register (DMA) rwl++++ A2A5L - HDMA Table Address low byte rwh++++ A2A5H - HDMA Table Address high byte aaaaaaaa aaaaaaaa At the beginning of the frame $4352/3 are copied into this register for all active HDMA channels, and then this register is updated as the table is read. Thus, if a game wishes to start HDMA mid-frame (or change tables mid-frame), this register must be written. Writing this register mid-frame changes the table address for the next scanline. This register is not used for DMA. This register is set to $FF on power on, and is unchanged on reset.
$435A 1 byte SNES Register (DMA) rwb++++ NLTR5 - HDMA Line Counter rccccccc r = Repeat Select. When set, the HDMA transfer will be performed every line, rather than only when this register is loaded from the table. However, this byte (and the indirect HDMA address) will only be reloaded from the table when the counter reaches 0. ccccccc = Line count. This is decremented every scanline. When it reaches 0, a byte is read from the HDMA table into this register (and the indirect HDMA address is read into $4355/6 if applicable). One oddity: the register is decremeted before being checked for r status or c==0. Thus, setting a value of $80 is really "128 lines with no repeat" rather than "0 lines with repeat". Similarly, a value of $00 will be "128 lines with repeat" when it doesn't mean "terminate the channel". This register is initialized at the end of V-Blank for every active HDMA channel. Note that if a game wishes to begin HDMA during the frame, it will most likely have to initalize this register. Writing this mid-transfer will similarly change the count and repeat to take effect next scanline. Remember though that 'repeat' won't take effect until after the next transfer period. This register is set to $ff on power on, and is unchanged on reset. See the section "DMA AND HDMA" below for more information. DMA and HDMA Information
$435B 2 bytes SNES Register (DMA) rwb++++ ????5 - Unknown rwb++++ ????5 - Unknown ???????? The effects of these registers (if any) are unknown. $435F and $435B are really aliases for the same register. This register is set to $FF on power on, and is unchanged on reset.
$4360 1 byte SNES Register (DMA) rwb++++ DMAP6 - DMA Control for Channel 6 da-ifttt d = Transfer Direction. When clear, data will be read from the CPU memory and written to the PPU register. When set, vice versa. Contrary to previous belief, this bit DOES affect HDMA! Indirect mode is more useful, it will read the table as normal and write from Bus B to the Bus A address specified. Direct mode will work as expected though, it will read counts from the table and try to write the data values into the table. a = HDMA Addressing Mode. When clear, the HDMA table contains the data to transfer. When set, the HDMA table contains pointers to the data. This bit does not affect DMA. i = DMA Address Increment. When clear, the DMA address will be incremented for each byte. When set, the DMA address will be decremented. This bit does not affect HDMA. f = DMA Fixed Transfer. When set, the DMA address will not be adjusted. When clear, the address will be adjusted as specified by bit 4. This bit does not affect HDMA. ttt = Transfer Mode. 000 => 1 register write once (1 byte: p ) 001 => 2 registers write once (2 bytes: p, p+1 ) 010 => 1 register write twice (2 bytes: p, p ) 011 => 2 registers write twice each (4 bytes: p, p, p+1, p+1) 100 => 4 registers write once (4 bytes: p, p+1, p+2, p+3) 101 => 2 registers write twice alternate (4 bytes: p, p+1, p, p+1) 110 => 1 register write twice (2 bytes: p, p ) 111 => 2 registers write twice each (4 bytes: p, p, p+1, p+1) The effect of writing this register during HDMA to the associated channel is unknown. Most likely, the change takes effect for the next HDMA transfer. This register is set to $FF on power on, and is unchanged on reset.
$4361 1 byte SNES Register (DMA) rwb++++ BBAD6 - DMA Destination Register for Channel 6 pppppppp This specifies the Bus B address to access. Considering the standard CPU memory space, this specifies which address $00:2100-$00:21FF to access, with two- and four-register modes wrapping $21FF->$2100, not $2200. The effect of writing this register during HDMA to the associated channel is unknown. Most likely, the change takes effect for the next transfer. This register is set to $FF on power on, and is unchanged on reset.
$4362 3 bytes SNES Register (DMA) rwl++++ A1T6L - DMA Source Address for Channel 6 low byte rwh++++ A1T6H - DMA Source Address for Channel 6 high byte rwb++++ A1B6 - DMA Source Address for Channel 6 bank byte bbbbbbbb hhhhhhhh llllllll This specifies the starting Address Bus A address for the DMA transfer, or the beginning of the HDMA table for HDMA transfers. Note that Bus A does not access the Bus B registers, so pointing this address at say $00:2100 results in open bus. The effect of writing this register during HDMA to the associated channel is unknown. However, current theory is that only $4364 will affect the transfer. The changes will take effect at the next HDMA init. During DMA, $4362/3 will be incremented or decremented as specified by $4362/3. However $4364 will NOT be adjusted. These registers will not be affected by HDMA. This register is set to $FF on power on, and is unchanged on reset.
$4365 3 bytes SNES Register (DMA) rwl++++ DAS6L - DMA Size/HDMA Indirect Address low byte rwh++++ DAS6H - DMA Size/HDMA Indirect Address high byte rwb++++ DASB6 - HDMA Indirect Address bank byte bbbbbbbb hhhhhhhh llllllll For DMA, $4365/6 indicate the number of bytes to transfer. Note that this is a strict limit: if this is set to 1 then only 1 byte will be written, even if the transfer mode specifies 2 or 4 registers (and if this is 5, all 4 registers would be written once, then the first only would be written a second time). Note, however, that writing $0000 to this register actually results in a transfer of $10000 bytes, not 0. $4365/6 are decremented during DMA, and thus typically end up set to 0 when DMA is complete. For HDMA, $4367 specifies the bank for indirect addressing mode. The indirect address is copied into $4365/6 and incremented appropriately. For direct HDMA, these registers are not used or altered. Writes to $4367 during indirect HDMA will take effect for the next transfer. Writes to $4365/6 during indirect HDMA will also take effect for the next HDMA transfer, however this is only noticable during repeat mode (for normal mode, a new indirect address will be read from the table before the transfer). For a direct transfer, presumably nothing will happen. This register is set to $FF on power on, and is unchanged on reset.
$4368 2 bytes SNES Register (DMA) rwl++++ A2A6L - HDMA Table Address low byte rwh++++ A2A6H - HDMA Table Address high byte aaaaaaaa aaaaaaaa At the beginning of the frame $4362/3 are copied into this register for all active HDMA channels, and then this register is updated as the table is read. Thus, if a game wishes to start HDMA mid-frame (or change tables mid-frame), this register must be written. Writing this register mid-frame changes the table address for the next scanline. This register is not used for DMA. This register is set to $FF on power on, and is unchanged on reset.
$436A 1 byte SNES Register (DMA) rwb++++ NLTR6 - HDMA Line Counter rccccccc r = Repeat Select. When set, the HDMA transfer will be performed every line, rather than only when this register is loaded from the table. However, this byte (and the indirect HDMA address) will only be reloaded from the table when the counter reaches 0. ccccccc = Line count. This is decremented every scanline. When it reaches 0, a byte is read from the HDMA table into this register (and the indirect HDMA address is read into $4365/6 if applicable). One oddity: the register is decremeted before being checked for r status or c==0. Thus, setting a value of $80 is really "128 lines with no repeat" rather than "0 lines with repeat". Similarly, a value of $00 will be "128 lines with repeat" when it doesn't mean "terminate the channel". This register is initialized at the end of V-Blank for every active HDMA channel. Note that if a game wishes to begin HDMA during the frame, it will most likely have to initalize this register. Writing this mid-transfer will similarly change the count and repeat to take effect next scanline. Remember though that 'repeat' won't take effect until after the next transfer period. This register is set to $ff on power on, and is unchanged on reset. See the section "DMA AND HDMA" below for more information. DMA and HDMA Information
$436B 2 bytes SNES Register (DMA) rwb++++ ????6 - Unknown rwb++++ ????6 - Unknown ???????? The effects of these registers (if any) are unknown. $436F and $436B are really aliases for the same register. This register is set to $FF on power on, and is unchanged on reset.
$4370 1 byte SNES Register (DMA) rwb++++ DMAP7 - DMA Control for Channel 7 da-ifttt d = Transfer Direction. When clear, data will be read from the CPU memory and written to the PPU register. When set, vice versa. Contrary to previous belief, this bit DOES affect HDMA! Indirect mode is more useful, it will read the table as normal and write from Bus B to the Bus A address specified. Direct mode will work as expected though, it will read counts from the table and try to write the data values into the table. a = HDMA Addressing Mode. When clear, the HDMA table contains the data to transfer. When set, the HDMA table contains pointers to the data. This bit does not affect DMA. i = DMA Address Increment. When clear, the DMA address will be incremented for each byte. When set, the DMA address will be decremented. This bit does not affect HDMA. f = DMA Fixed Transfer. When set, the DMA address will not be adjusted. When clear, the address will be adjusted as specified by bit 4. This bit does not affect HDMA. ttt = Transfer Mode. 000 => 1 register write once (1 byte: p ) 001 => 2 registers write once (2 bytes: p, p+1 ) 010 => 1 register write twice (2 bytes: p, p ) 011 => 2 registers write twice each (4 bytes: p, p, p+1, p+1) 100 => 4 registers write once (4 bytes: p, p+1, p+2, p+3) 101 => 2 registers write twice alternate (4 bytes: p, p+1, p, p+1) 110 => 1 register write twice (2 bytes: p, p ) 111 => 2 registers write twice each (4 bytes: p, p, p+1, p+1) The effect of writing this register during HDMA to the associated channel is unknown. Most likely, the change takes effect for the next HDMA transfer. This register is set to $FF on power on, and is unchanged on reset.
$4371 1 byte SNES Register (DMA) rwb++++ BBAD7 - DMA Destination Register for Channel 7 pppppppp This specifies the Bus B address to access. Considering the standard CPU memory space, this specifies which address $00:2100-$00:21FF to access, with two- and four-register modes wrapping $21FF->$2100, not $2200. The effect of writing this register during HDMA to the associated channel is unknown. Most likely, the change takes effect for the next transfer. This register is set to $FF on power on, and is unchanged on reset.
$4372 3 bytes SNES Register (DMA) rwl++++ A1T7L - DMA Source Address for Channel 7 low byte rwh++++ A1T7H - DMA Source Address for Channel 7 high byte rwb++++ A1B7 - DMA Source Address for Channel 7 bank byte bbbbbbbb hhhhhhhh llllllll This specifies the starting Address Bus A address for the DMA transfer, or the beginning of the HDMA table for HDMA transfers. Note that Bus A does not access the Bus B registers, so pointing this address at say $00:2100 results in open bus. The effect of writing this register during HDMA to the associated channel is unknown. However, current theory is that only $4374 will affect the transfer. The changes will take effect at the next HDMA init. During DMA, $4372/3 will be incremented or decremented as specified by $4372/3. However $4374 will NOT be adjusted. These registers will not be affected by HDMA. This register is set to $FF on power on, and is unchanged on reset.
$4375 3 bytes SNES Register (DMA) rwl++++ DAS7L - DMA Size/HDMA Indirect Address low byte rwh++++ DAS7H - DMA Size/HDMA Indirect Address high byte rwb++++ DASB7 - HDMA Indirect Address bank byte bbbbbbbb hhhhhhhh llllllll For DMA, $4375/6 indicate the number of bytes to transfer. Note that this is a strict limit: if this is set to 1 then only 1 byte will be written, even if the transfer mode specifies 2 or 4 registers (and if this is 5, all 4 registers would be written once, then the first only would be written a second time). Note, however, that writing $0000 to this register actually results in a transfer of $10000 bytes, not 0. $4375/6 are decremented during DMA, and thus typically end up set to 0 when DMA is complete. For HDMA, $4377 specifies the bank for indirect addressing mode. The indirect address is copied into $4375/6 and incremented appropriately. For direct HDMA, these registers are not used or altered. Writes to $4377 during indirect HDMA will take effect for the next transfer. Writes to $4375/6 during indirect HDMA will also take effect for the next HDMA transfer, however this is only noticable during repeat mode (for normal mode, a new indirect address will be read from the table before the transfer). For a direct transfer, presumably nothing will happen. This register is set to $FF on power on, and is unchanged on reset.
$4378 2 bytes SNES Register (DMA) rwl++++ A2A7L - HDMA Table Address low byte rwh++++ A2A7H - HDMA Table Address high byte aaaaaaaa aaaaaaaa At the beginning of the frame $4372/3 are copied into this register for all active HDMA channels, and then this register is updated as the table is read. Thus, if a game wishes to start HDMA mid-frame (or change tables mid-frame), this register must be written. Writing this register mid-frame changes the table address for the next scanline. This register is not used for DMA. This register is set to $FF on power on, and is unchanged on reset.
$437A 1 byte SNES Register (DMA) rwb++++ NLTR7 - HDMA Line Counter rccccccc r = Repeat Select. When set, the HDMA transfer will be performed every line, rather than only when this register is loaded from the table. However, this byte (and the indirect HDMA address) will only be reloaded from the table when the counter reaches 0. ccccccc = Line count. This is decremented every scanline. When it reaches 0, a byte is read from the HDMA table into this register (and the indirect HDMA address is read into $4375/6 if applicable). One oddity: the register is decremeted before being checked for r status or c==0. Thus, setting a value of $80 is really "128 lines with no repeat" rather than "0 lines with repeat". Similarly, a value of $00 will be "128 lines with repeat" when it doesn't mean "terminate the channel". This register is initialized at the end of V-Blank for every active HDMA channel. Note that if a game wishes to begin HDMA during the frame, it will most likely have to initalize this register. Writing this mid-transfer will similarly change the count and repeat to take effect next scanline. Remember though that 'repeat' won't take effect until after the next transfer period. This register is set to $ff on power on, and is unchanged on reset. See the section "DMA AND HDMA" below for more information. DMA and HDMA Information
$437B 2 bytes SNES Register (DMA) rwb++++ ????7 - Unknown rwb++++ ????7 - Unknown ???????? The effects of these registers (if any) are unknown. $437F and $437B are really aliases for the same register. This register is set to $FF on power on, and is unchanged on reset.
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