YI Memory Map
Displaying 427 out of 1427 addresses.
View: moderated | waiting (27)
ROM Address | Length | Type | Description | Details |
---|---|---|---|---|
$3AB51B | 1354 bytes | Graphics | LC_LZ16 file $010: 4bpp, 4kb | |
$3ABA65 | 1301 bytes | Graphics | LC_LZ16 file $011: 4bpp, 4kb | |
$3ABF7A | 214 bytes | Graphics | LC_LZ16 file $012: 4bpp, 1kb | |
$3AC050 | 1664 bytes | Graphics | LC_LZ16 file $013: 4bpp, 4kb | |
$3AC6D0 | 1219 bytes | Graphics | LC_LZ16 file $014: 4bpp, 4kb | |
$3ACB93 | 1418 bytes | Graphics | LC_LZ16 file $015: 4bpp, 4kb | |
$3AD11D | 1745 bytes | Graphics | LC_LZ16 file $016: 4bpp, 4kb | |
$3AD7EE | 1356 bytes | Graphics | LC_LZ16 file $017: 4bpp, 4kb | |
$3ADD3A | 1839 bytes | Graphics | LC_LZ16 file $018: 4bpp, 4kb | |
$3AE469 | 1638 bytes | Graphics | LC_LZ16 file $019: 4bpp, 4kb | |
$3AEACF | 458 bytes | Graphics | LC_LZ16 file $01A: 4bpp, 1kb | |
$3AEC99 | 275 bytes | Graphics | LC_LZ16 file $01B: 4bpp, 1kb | |
$3AEDAC | 246 bytes | Graphics | LC_LZ16 file $01C: 4bpp, 1kb | |
$3AEEA2 | 401 bytes | Graphics | LC_LZ16 file $01D: 4bpp, 1kb | |
$3AF033 | 600 bytes | Graphics | LC_LZ16 file $01E: 4bpp, 1kb | |
$3AF28B | 475 bytes | Graphics | LC_LZ16 file $01F: 4bpp, 1kb | |
$3AF466 | 445 bytes | Graphics | LC_LZ16 file $020: 4bpp, 1kb | |
$3AF623 | 493 bytes | Graphics | LC_LZ16 file $021: 4bpp, 1kb | |
$3AF810 | 427 bytes | Graphics | LC_LZ16 file $022: 4bpp, 1kb | |
$3AF9BB | 373 bytes | Graphics | LC_LZ16 file $023: 4bpp, 1kb | |
$3AFB30 | 341 bytes | Graphics | LC_LZ16 file $024: 4bpp, 1kb | |
$3AFC85 | 466 bytes | Graphics | LC_LZ16 file $025: 4bpp, 1kb | |
$3AFE57 | 588 bytes | Graphics | LC_LZ16 file $026: 4bpp, 1kb | |
$3B80A3 | 549 bytes | Graphics | LC_LZ16 file $027: 4bpp, 1kb | |
$3B82C8 | 403 bytes | Graphics | LC_LZ16 file $028: 4bpp, 1kb | |
$3B845B | 601 bytes | Graphics | LC_LZ16 file $029: 4bpp, 1kb | |
$3B86B4 | 324 bytes | Graphics | LC_LZ16 file $02A: 4bpp, 1kb | |
$3B87F8 | 408 bytes | Graphics | LC_LZ16 file $02B: 4bpp, 1kb | |
$3B8990 | 435 bytes | Graphics | LC_LZ16 file $02C: 4bpp, 1kb | |
$3B8B43 | 490 bytes | Graphics | LC_LZ16 file $02D: 4bpp, 1kb | |
$3B8D2D | 316 bytes | Graphics | LC_LZ16 file $02E: 4bpp, 1kb | |
$3B8E69 | 349 bytes | Graphics | LC_LZ16 file $02F: 4bpp, 1kb | |
$3B8FC6 | 306 bytes | Graphics | LC_LZ16 file $030: 4bpp, 1kb | |
$3B90F8 | 330 bytes | Graphics | LC_LZ16 file $031: 4bpp, 1kb | |
$3B9242 | 379 bytes | Graphics | LC_LZ16 file $032: 4bpp, 1kb | |
$3B93BD | 365 bytes | Graphics | LC_LZ16 file $033: 4bpp, 1kb | |
$3B952A | 370 bytes | Graphics | LC_LZ16 file $034: 4bpp, 1kb | |
$3B969C | 596 bytes | Graphics | LC_LZ16 file $035: 4bpp, 1kb | |
$3B98F0 | 508 bytes | Graphics | LC_LZ16 file $036: 4bpp, 1kb | |
$3B9AEC | 349 bytes | Graphics | LC_LZ16 file $037: 4bpp, 1kb | |
$3B9C49 | 381 bytes | Graphics | LC_LZ16 file $038: 4bpp, 1kb | |
$3B9DC6 | 564 bytes | Graphics | LC_LZ16 file $039: 4bpp, 1kb | |
$3B9FFA | 407 bytes | Graphics | LC_LZ16 file $03A: 4bpp, 1kb | |
$3BA191 | 504 bytes | Graphics | LC_LZ16 file $03B: 4bpp, 1kb | |
$3BA389 | 429 bytes | Graphics | LC_LZ16 file $03C: 4bpp, 1kb | |
$3BA536 | 478 bytes | Graphics | LC_LZ16 file $03D: 4bpp, 1kb | |
$3BA714 | 588 bytes | Graphics | LC_LZ16 file $03E: 4bpp, 1kb | |
$3BA960 | 505 bytes | Graphics | LC_LZ16 file $03F: 4bpp, 1kb | |
$3BAB59 | 408 bytes | Graphics | LC_LZ16 file $040: 4bpp, 1kb | |
$3BACF1 | 387 bytes | Graphics | LC_LZ16 file $041: 4bpp, 1kb | |
$3BAE74 | 326 bytes | Graphics | LC_LZ16 file $042: 4bpp, 1kb | |
$3BAFBA | 313 bytes | Graphics | LC_LZ16 file $043: 4bpp, 1kb | |
$3BB0F3 | 558 bytes | Graphics | LC_LZ16 file $044: 4bpp, 1kb | |
$3BB321 | 362 bytes | Graphics | LC_LZ16 file $045: 4bpp, 1kb | |
$3BB48B | 357 bytes | Graphics | LC_LZ16 file $046: 4bpp, 1kb | |
$3BB5F0 | 542 bytes | Graphics | LC_LZ16 file $047: 4bpp, 1kb | |
$3BB80E | 560 bytes | Graphics | LC_LZ16 file $048: 4bpp, 1kb | |
$3BBA3E | 483 bytes | Graphics | LC_LZ16 file $049: 4bpp, 1kb | |
$3BBC21 | 416 bytes | Graphics | LC_LZ16 file $04A: 4bpp, 1kb | |
$3BBDC1 | 363 bytes | Graphics | LC_LZ16 file $04B: 4bpp, 1kb | |
$3BBF2C | 435 bytes | Graphics | LC_LZ16 file $04C: 4bpp, 1kb | |
$3BC0DF | 269 bytes | Graphics | LC_LZ16 file $04D: 4bpp, 1kb | |
$3BC1EC | 515 bytes | Graphics | LC_LZ16 file $04E: 4bpp, 1kb | |
$3BC3EF | 413 bytes | Graphics | LC_LZ16 file $04F: 4bpp, 1kb | |
$3BC58C | 383 bytes | Graphics | LC_LZ16 file $050: 4bpp, 1kb | |
$3BC70B | 378 bytes | Graphics | LC_LZ16 file $051: 4bpp, 1kb | |
$3BC885 | 194 bytes | Graphics | LC_LZ16 file $052: 4bpp, 1kb | |
$3BC947 | 247 bytes | Graphics | LC_LZ16 file $053: 4bpp, 1kb | |
$3BCA3E | 496 bytes | Graphics | LC_LZ16 file $054: 4bpp, 1kb | |
$3BCC2E | 509 bytes | Graphics | LC_LZ16 file $055: 4bpp, 1kb | |
$3BCE2B | 436 bytes | Graphics | LC_LZ16 file $056: 4bpp, 1kb | |
$3BCFDF | 314 bytes | Graphics | LC_LZ16 file $057: 4bpp, 1kb | |
$3BD119 | 365 bytes | Graphics | LC_LZ16 file $058: 4bpp, 1kb | |
$3BD286 | 447 bytes | Graphics | LC_LZ16 file $059: 4bpp, 1kb | |
$3BD445 | 438 bytes | Graphics | LC_LZ16 file $05A: 4bpp, 1kb | |
$3BD5FB | 459 bytes | Graphics | LC_LZ16 file $05B: 4bpp, 1kb | |
$3BD7C6 | 362 bytes | Graphics | LC_LZ16 file $05C: 4bpp, 1kb | |
$3BD930 | 452 bytes | Graphics | LC_LZ16 file $05D: 4bpp, 1kb | |
$3BDAF4 | 474 bytes | Graphics | LC_LZ16 file $05E: 4bpp, 1kb | |
$3BDCCE | 322 bytes | Graphics | LC_LZ16 file $05F: 4bpp, 1kb | |
$3BDE10 | 416 bytes | Graphics | LC_LZ16 file $060: 4bpp, 1kb | |
$3BDFB0 | 312 bytes | Graphics | LC_LZ16 file $061: 4bpp, 1kb | |
$3BE0E8 | 244 bytes | Graphics | LC_LZ16 file $062: 4bpp, 1kb | |
$3BE1DC | 457 bytes | Graphics | LC_LZ16 file $063: 4bpp, 1kb | |
$3BE3A5 | 476 bytes | Graphics | LC_LZ16 file $064: 4bpp, 1kb | |
$3BE581 | 360 bytes | Graphics | LC_LZ16 file $065: 4bpp, 1kb | |
$3BE6E9 | 453 bytes | Graphics | LC_LZ16 file $066: 4bpp, 1kb | |
$3BE8AE | 421 bytes | Graphics | LC_LZ16 file $067: 4bpp, 1kb | |
$3BEA53 | 505 bytes | Graphics | LC_LZ16 file $068: 4bpp, 1kb | |
$3BEC4C | 424 bytes | Graphics | LC_LZ16 file $069: 4bpp, 1kb | |
$3BEDF4 | 470 bytes | Graphics | LC_LZ16 file $06A: 4bpp, 1kb | |
$3BEFCA | 371 bytes | Graphics | LC_LZ16 file $06B: 4bpp, 1kb | |
$3BF13D | 390 bytes | Graphics | LC_LZ16 file $06C: 4bpp, 1kb | |
$3BF2C3 | 214 bytes | Graphics | LC_LZ16 file $06D: 4bpp, 1kb | |
$3BF399 | 293 bytes | Graphics | LC_LZ16 file $06E: 4bpp, 1kb | |
$3BF4BE | 232 bytes | Graphics | LC_LZ16 file $06F: 4bpp, 1kb | |
$3BF5A6 | 356 bytes | Graphics | LC_LZ16 file $070: 4bpp, 1kb | |
$3BF70A | 250 bytes | Graphics | LC_LZ16 file $071: 4bpp, 1kb | |
$3BF804 | 3023 bytes | Graphics | LC_LZ16 file $072: 4bpp, 8kb | |
$3C83D3 | 451 bytes | Graphics | LC_LZ16 file $073: 4bpp, 2kb | |
$3C8596 | 442 bytes | Graphics | LC_LZ16 file $074: 4bpp, 2kb | |
$3C8750 | 518 bytes | Graphics | LC_LZ16 file $075: 4bpp, 2kb | |
$3C8956 | 352 bytes | Graphics | LC_LZ16 file $076: 4bpp, 2kb | |
$3C8AB6 | 1146 bytes | Graphics | LC_LZ16 file $077: 4bpp, 4kb | |
$3C8F30 | 1994 bytes | Graphics | LC_LZ16 file $078: 4bpp, 4kb | |
$3C96FA | 1751 bytes | Graphics | LC_LZ16 file $079: 4bpp, 4kb | |
$3C9DD1 | 1663 bytes | Graphics | LC_LZ16 file $07A: 4bpp, 4kb | |
$3CA450 | 2543 bytes | Graphics | LC_LZ16 file $07B: 4bpp, 4kb | |
$3CAE3F | 2810 bytes | Graphics | LC_LZ16 file $07C: 4bpp, 4kb | |
$3CB939 | 1245 bytes | Graphics | LC_LZ16 file $07D: 4bpp, 4kb | |
$3CBE16 | 1174 bytes | Graphics | LC_LZ16 file $07E: 4bpp, 4kb | |
$3CC2AC | 2729 bytes | Graphics | LC_LZ16 file $07F: 4bpp, 4kb | |
$3CCD55 | 2642 bytes | Graphics | LC_LZ16 file $080: 4bpp, 4kb | |
$3CD7A7 | 1700 bytes | Graphics | LC_LZ16 file $081: 4bpp, 4kb | |
$3CDE4B | 1848 bytes | Graphics | LC_LZ16 file $082: 4bpp, 4kb | |
$3CE583 | 1323 bytes | Graphics | LC_LZ16 file $083: 4bpp, 4kb | |
$3CEAAE | 1586 bytes | Graphics | LC_LZ16 file $084: 4bpp, 4kb | |
$3CF0E0 | 1821 bytes | Graphics | LC_LZ16 file $085: 4bpp, 4kb | |
$3CF7FD | 2722 bytes | Graphics | LC_LZ16 file $086: 4bpp, 4kb | |
$3D829F | 4289 bytes | Graphics | LC_LZ16 file $087: 4bpp, 8kb | |
$3D9360 | 5216 bytes | Graphics | LC_LZ16 file $088: 4bpp, 8kb | |
$3DA7C0 | 4705 bytes | Graphics | LC_LZ16 file $089: 4bpp, 8kb | |
$3DBA21 | 3096 bytes | Graphics | LC_LZ16 file $08A: 4bpp, 8kb | |
$3DC639 | 2846 bytes | Graphics | LC_LZ16 file $08B: 4bpp, 8kb | |
$3DD157 | 1639 bytes | Graphics | LC_LZ16 file $08C: 4bpp, 4kb | |
$3DD7BE | 3092 bytes | Graphics | LC_LZ16 file $08D: 4bpp, 4kb | |
$3DE3D2 | 1479 bytes | Graphics | LC_LZ16 file $08E: 4bpp, 4kb | |
$3DE999 | 751 bytes | Graphics | LC_LZ16 file $08F: 4bpp, 4kb | |
$3DEC88 | 1833 bytes | Graphics | LC_LZ16 file $090: 4bpp, 4kb | |
$3DF3B1 | 555 bytes | Graphics | LC_LZ16 file $091: 4bpp, 2kb | |
$3DF5DC | 617 bytes | Graphics | LC_LZ16 file $092: 4bpp, 2kb | |
$3DF845 | 553 bytes | Graphics | LC_LZ16 file $093: 4bpp, 2kb | |
$3DFA6E | 616 bytes | Graphics | LC_LZ16 file $094: 4bpp, 2kb | |
$3DFCD6 | 553 bytes | Graphics | LC_LZ16 file $095: 4bpp, 2kb | |
$3DFEFF | 767 bytes | Graphics | LC_LZ16 file $096: 4bpp, 2kb | |
$3E81FE | 888 bytes | Graphics | LC_LZ16 file $097: 4bpp, 2kb | |
$3E8576 | 940 bytes | Graphics | LC_LZ16 file $098: 4bpp, 2kb | |
$3E8922 | 665 bytes | Graphics | LC_LZ16 file $099: 4bpp, 2kb | |
$3E8BBB | 1318 bytes | Graphics | LC_LZ16 file $09A: 4bpp, 2kb | |
$3E90E1 | 1241 bytes | Graphics | LC_LZ16 file $09B: 4bpp, 2kb | |
$3E95BA | 934 bytes | Graphics | LC_LZ16 file $09C: 4bpp, 2kb | |
$3E9960 | 1079 bytes | Graphics | LC_LZ16 file $09D: 4bpp, 2kb | |
$3E9D97 | 1044 bytes | Graphics | LC_LZ16 file $09E: 4bpp, 2kb | |
$3EA1AB | 1104 bytes | Graphics | LC_LZ16 file $09F: 4bpp, 2kb | |
$3EA5FB | 845 bytes | Graphics | LC_LZ16 file $0A0: 4bpp, 2kb | |
$3EA948 | 868 bytes | Graphics | LC_LZ16 file $0A1: 4bpp, 4kb | |
$3EACAC | 516 bytes | Graphics | LC_LZ16 file $0A2: 4bpp, 4kb | |
$3EAEB0 | 1186 bytes | Graphics | LC_LZ16 file $0A3: 4bpp, 4kb | |
$3EB352 | 1822 bytes | Graphics | LC_LZ16 file $0A4: 4bpp, 4kb | |
$3EBA70 | 1443 bytes | Graphics | LC_LZ16 file $0A5: 4bpp, 4kb | |
$3EC013 | 1444 bytes | Graphics | LC_LZ16 file $0A6: 4bpp, 4kb | |
$3EC5B7 | 1969 bytes | Graphics | LC_LZ16 file $0A7: 4bpp, 4kb | |
$3ECD68 | 1821 bytes | Graphics | LC_LZ16 file $0A8: 4bpp, 4kb | |
$3ED485 | 338 bytes | Graphics | LC_LZ16 file $0A9: 4bpp, 1kb | |
$3ED5D7 | 363 bytes | Graphics | LC_LZ16 file $0AA: 4bpp, 1kb | |
$3ED742 | 512 bytes | Graphics | LC_LZ16 file $0AB: 4bpp, 1kb | |
$3ED942 | 592 bytes | Graphics | LC_LZ16 file $0AC: 4bpp, 1kb | |
$3EDB92 | 438 bytes | Graphics | LC_LZ16 file $0AD: 4bpp, 1kb | |
$3EDD48 | 473 bytes | Graphics | LC_LZ16 file $0AE: 4bpp, 1kb | |
$3EDF21 | 517 bytes | Graphics | LC_LZ16 file $0AF: 4bpp, 1kb | |
$3EE126 | 428 bytes | Graphics | LC_LZ16 file $0B0: 4bpp, 1kb | |
$3EE2D2 | 1619 bytes | Graphics | LC_LZ16 file $0B1: 4bpp, 4kb | |
$3EE925 | 1379 bytes | Graphics | LC_LZ16 file $0B2: 4bpp, 4kb | |
$3EEE88 | 980 bytes | Graphics | LC_LZ16 file $0B3: 4bpp, 4kb | |
$3EF25C | 1706 bytes | Graphics | LC_LZ16 file $0B4: 4bpp, 4kb | |
$3EF906 | 451 bytes | Graphics | LC_LZ16 file $0B5: 4bpp, 2kb | |
$3EFAC9 | 536 bytes | Graphics | LC_LZ16 file $0B6: 4bpp, 2kb | |
$3EFCE1 | 453 bytes | Graphics | LC_LZ16 file $0B7: 4bpp, 2kb | |
$3EFEA6 | 530 bytes | Graphics | LC_LZ16 file $0B8: 4bpp, 2kb | |
$3F80B8 | 1233 bytes | Graphics | LC_LZ16 file $0B9: 4bpp, 4kb | |
$3F8589 | 1197 bytes | Graphics | LC_LZ16 file $0BA: 4bpp, 4kb | |
$3F8A36 | 2378 bytes | Empty | Empty (filled with FF) | |
$3F9380 | 1152 bytes | Misc. Tilemap | Tilemap of title screen sky | |
$3F9800 | 1024 bytes | Misc. Tilemap | Tilemap of the title screen island (worlds 1-5) | |
$3F9C00 | 1024 bytes | Misc. Tilemap | Tilemap of the title screen island (world 6) | |
$3FA000 | 24576 bytes | Object Palette | CGRAM/palette color data | |
$3FD64C | 48 bytes | Misc. | Color Gradient for BG Back Area color header $10 Table ordered from bottom to top of sublevel Each color has 15 scanlines between them interpolated 24 word entries: Word: 0BBBBBGG GGGRRRRR |
|
Regs Address | Length | Type | Description | Details |
$2100 | 1 byte | SNES Register (PPU) | wb++++ INIDISP - Screen Display x---bbbb x = Force blank on when set. bbbb = Screen brightness, F=max, 0="off". Note that force blank CAN be disabled mid-scanline. However, this can result in glitched graphics on that scanline, as the internal rendering buffers will not have been updated during force blank. Current theory is that BGs will be glitched for a few tiles (depending on how far in advance the PPU operates), and OBJ will be glitched for the entire scanline. Also, writing this register on the first line of V-Blank (225 or 240, depending on overscan) when force blank is currently active causes the OAM Address Reset to occur. | |
$2101 | 1 byte | SNES Register (PPU) | wb++?- OBSEL - Object Size and Chr Address sssnnbbb sss = Object size: 000 = 8x8 and 16x16 sprites 001 = 8x8 and 32x32 sprites 010 = 8x8 and 64x64 sprites 011 = 16x16 and 32x32 sprites 100 = 16x16 and 64x64 sprites 101 = 32x32 and 64x64 sprites 110 = 16x32 and 32x64 sprites ('undocumented') 111 = 16x32 and 32x32 sprites ('undocumented') nn = Name Select bbb = Name Base Select (Addr>>14) See the section "SPRITES" below for details. | Sprite Information |
$2102 | 2 bytes | SNES Register (PPU) | wl++?- OAMADDL - OAM Address low byte wh++?- OAMADDH - OAM Address high bit and Obj Priority p------b aaaaaaaa p = Obj Priority activation bit When this bit is set, an Obj other than Sprite 0 may be given priority. See the section "SPRITES" below for details. b aaaaaaaa = OAM address This can be thought of in two ways, depending on your conception of OAM. If you consider OAM as a 544-byte table, baaaaaaaa is the word address into that table. If you consider OAM to be a 512-byte table and a 32-byte table, b is the table selector and aaaaaaaa is the word address in the table. See the section "SPRITES" below for details. The internal OAM address is invalidated when scanlines are being rendered. This invalidation is deterministic, but we do not know how it is determined. Thus, the last value written to these registers is reloaded into the internal OAM address at the beginning of V-Blank if that occurs outside of a force-blank period. This is known as 'OAM reset'. 'OAM reset' also occurs on certain writes to $2100. Writing to either $2102 or $2103 resets the entire internal OAM Address to the values last written to this register. E.g., if you set $104 to this register, write 4 bytes, then write $1 to $2103, the internal OAM address will point to word 4, not word 6. | Sprite Information |
$2104 | 1 byte | SNES Register (PPU) | wb++-- OAMDATA - Data for OAM write dddddddd Note that OAM writes are done in an odd manner, in particular the low table of OAM is not affected until the high byte of a word is written (however, the high table is affected immediately). Thus, if you set the address, then alternate writes and reads, OAM will never be affected until you reach the high table! Similarly, if you set the address to 0, then write 1, 2, read, then write 3, OAM will end up as "01 02 01 03", rather than "01 02 xx 03" as you might expect. Technically, this register CAN be written during H-blank (and probably mid-scanline as well). However, due to OAM address invalidation, the actual OAM byte written will probably not be what you expect. Note that writing during force-blank will only work as expected if that force-blank was begun during V-Blank, or (probably) if $2102/3 have been reset during that force-blank period. See the section "SPRITES" below for details. | Sprite Information |
$2105 | 1 byte | SNES Register (PPU) | wb+++- BGMODE - BG Mode and Character Size DCBAemmm A/B/C/D = BG character size for BG1/BG2/BG3/BG4 If the bit is set, then the BG is made of 16x16 tiles. Otherwise, 8x8 tiles are used. However, note that Modes 5 and 6 always use 16-pixel wide tiles, and Mode 7 always uses 8x8 tiles. See the section "BACKGROUNDS" below for details. mmm = BG Mode e = Mode 1 BG3 priority bit Mode BG depth OPT Priorities 1 2 3 4 Front -> Back -=-------=-=-=-=----=---============--- 0 2 2 2 2 n 3AB2ab1CD0cd 1 4 4 2 n 3AB2ab1C 0c * if e set: C3AB2ab1 0c 2 4 4 y 3A 2B 1a 0b 3 8 4 n 3A 2B 1a 0b 4 8 2 y 3A 2B 1a 0b 5 4 2 n 3A 2B 1a 0b 6 4 y 3A 2 1a 0 7 8 n 3 2 1a 0 7+EXTBG 8 7 n 3 2B 1a 0b "OPT" means "Offset-per-tile mode". For the priorities, numbers mean sprites with that priority. Letters correspond to BGs (A=1, B=2, etc), with upper/lower case indicating tile priority 1/0. See the section "BACKGROUNDS" below for details. Mode 7's EXTBG mode allows you to enable BG2, which uses the same tilemap and character data as BG1 but interprets bit 7 of the pixel data as a priority bit. BG2 also has some oddness to do with some of the per-BG registers below. See the Mode 7 section under BACKGROUNDS for details. | |
$2106 | 1 byte | SNES Register (PPU) | wb+++- MOSAIC - Screen Pixelation xxxxDCBA A/B/C/D = Affect BG1/BG2/BG3/BG4 xxxx = pixel size, 0=1x1, F=16x16 The mosaic filter goes over the BG and covers each x-by-x square with the upper-left pixel of that square, with the top of the first row of squares on the 'starting scanline'. If this register is set during the frame, the 'starting scanline' is the current scanline, otherwise it is the first visible scanline of the frame. I.e. if even scanlines are completely red and odd scanlines are completely blue, setting the xxxx=1 mid-frame will make the rest of the screen either completely red or completely blue depending on whether you set xxxx on an even or an odd scanline. XXX: It seems that writing the same value to this register does not reset the 'starting scanline', but which changes do reset it? Note that mosaic is applied after scrolling, but before any clip windows, color windows, or math. So the XxX block can be partially clipped, and it can be mathed as normal with a non-mosaiced BG. But scrolling can't make it partially one color and partially another. Modes 5-6 should 'double' the expansion factor to expand half-pixels. This actually makes xxxx=0 have a visible effect, since the even half-pixels (usually on the subscreen) hide the odd half-pixels. The same thing happens vertically with interlace mode. Mode 7, of course, is weird. BG1 mosaics about like normal, as long as you remember that the Mode 7 transformations have no effect on the XxX blocks. BG2 uses bit A to control 'vertical mosaic' and bit B to control 'horizontal mosaic', so you could be expanding over 1xX, Xx1, or XxX blocks. This can get really interesting as BG1 still uses bit A as normal, so you could have the BG1 pixels expanded XxX with high-priority BG2 pixels expanded 1xX on top of them. See the section "BACKGROUNDS" below for details. | Background Information |
$2107 | 4 bytes | SNES Register (PPU) | wb++?- BG1SC - BG1 Tilemap Address and Size wb++?- BG2SC - BG2 Tilemap Address and Size wb++?- BG3SC - BG3 Tilemap Address and Size wb++?- BG4SC - BG4 Tilemap Address and Size aaaaaayx aaaaaa = Tilemap address in VRAM (Addr>>10) x = Tilemap horizontal mirroring y = Tilemap veritcal mirroring All tilemaps are 32x32 tiles. If x and y are both unset, there is one tilemap at Addr. If x is set, a second tilemap follows the first that should be considered "to the right of" the first. If y is set, a second tilemap follows the first that should be considered "below" the first. If both are set, then a second follows "to the right", then a third "below", and a fourth "below and to the right". See the section "BACKGROUNDS" below for more details. | Background Information |
$210B | 2 bytes | SNES Register (PPU) | wb++?- BG12NBA - BG1 and 2 Chr Address wb++?- BG34NBA - BG3 and 4 Chr Address bbbbaaaa aaaa = Base address for BG1/3 (Addr>>13) bbbb = Base address for BG2/4 (Addr>>13) See the section "BACKGROUNDS" below for details. | Background Information |
$210D | 4 bytes | SNES Register (PPU) | ww+++- BG1HOFS - BG1 Horizontal Scroll ww+++- M7HOFS - Mode 7 BG Horizontal Scroll ww+++- BG1VOFS - BG1 Vertical Scroll ww+++- M7VOFS - Mode 7 BG Vertical Scroll ------xx xxxxxxxx ---mmmmm mmmmmmmm x = The BG offset, 10 bits. m = The Mode 7 BG offset, 13 bits two's-complement signed. These are actually two registers in one (or would that be "4 registers in 2"?). Anyway, writing $210d will write both BG1HOFS which works exactly like the rest of the BGnxOFS registers below ($210f-$2114), and M7HOFS which works with the M7* registers ($211b-$2120) instead. Modes 0-6 use BG1xOFS and ignore M7xOFS, while Mode 7 uses M7xOFS and ignores BG1HOFS. See the appropriate sections below for details, and note the different formulas for BG1HOFS versus M7HOFS. |
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$210F | 6 bytes | SNES Register (PPU) | ww+++- BG2HOFS - BG2 Horizontal Scroll ww+++- BG2VOFS - BG2 Vertical Scroll ww+++- BG3HOFS - BG3 Horizontal Scroll ww+++- BG3VOFS - BG3 Vertical Scroll ww+++- BG4HOFS - BG4 Horizontal Scroll ww+++- BG4VOFS - BG4 Vertical Scroll ------xx xxxxxxxx Note that these are "write twice" registers, first the low byte is written then the high. Current theory is that writes to the register work like this: BGnHOFS = (Current<<8) | (Prev&~7) | ((Reg>>8)&7); Prev = Current; or BGnVOFS = (Current<<8) | Prev; Prev = Current; Note that there is only one Prev shared by all the BGnxOFS registers. This is NOT shared with the M7* registers (not even M7xOFS and BG1xOFS). x = The BG offset, at most 10 bits (some modes effectively use as few as 8). Note that all BGs wrap if you try to go past their edges. Thus, the maximum offset value in BG Modes 0-6 is 1023, since you have at most 64 tiles (if x/y of BGnSC is set) of 16 pixels each (if the appropriate bit of BGMODE is set). Horizontal scrolling scrolls in units of full pixels no matter if we're rendering a 256-pixel wide screen or a 512-half-pixel wide screen. However, vertical scrolling will move in half-line increments if interlace mode is active. See the section "BACKGROUNDS" below for details. | Background Information |
$2115 | 1 byte | SNES Register (PPU) | wb++?- VMAIN - Video Port Control i---mmii i = Address increment mode: 0 => increment after writing $2118/reading $2139 1 => increment after writing $2119/reading $213a Note that a word write stores low first, then high. Thus, if you're storing a word value to $2118/9, you'll probably want to set 1 here. ii = Address increment amount 00 = Normal increment by 1 01 = Increment by 32 10 = Increment by 128 11 = Increment by 128 mm = Address remapping 00 = No remapping 01 = Remap addressing aaaaaaaaBBBccccc => aaaaaaaacccccBBB 10 = Remap addressing aaaaaaaBBBcccccc => aaaaaaaccccccBBB 11 = Remap addressing aaaaaaBBBccccccc => aaaaaacccccccBBB The "remap" modes basically implement address translation. If $2116/7 are set to #$0003, then word address #$0018 will be written instead, and $2116/7 will be incremented to $0004. | |
$2116 | 2 bytes | SNES Register (PPU) | wl++?- VMADDL - VRAM Address low byte wh++?- VMADDH - VRAM Address high byte aaaaaaaa aaaaaaaa This sets the address for $2118/9 and $2139/a. Note that this is a word address, not a byte address! See the sections "BACKGROUNDS" and "SPRITES" below for details. | Background Information Sprite Information |
$2118 | 2 bytes | SNES Register (PPU) | wl++-- VMDATAL - VRAM Data Write low byte wh++-- VMDATAH - VRAM Data Write high byte xxxxxxxx xxxxxxxx This writes data to VRAM. The writes take effect immediately(?), even if no increment is performed. The address is incremented when one of the two bytes is written; which one depends on the setting of bit 7 of register $2115. Keep in mind the address translation bits of $2115 as well. The interaction between these registers and $2139/a is unknown. See the sections "BACKGROUNDS" and "SPRITES" below for details. | Background Information Sprite Information |
$211A | 1 byte | SNES Register (PPU) | wb++?- M7SEL - Mode 7 Settings rc----yx r = Playing field size: When clear, the playing field is 1024x1024 pixels (so the tilemap completely fills it). When set, the playing field is much larger, and the 'empty space' fill is controlled by bit 6. c = Empty space fill, when bit 7 is set: 0 = Transparent. 1 = Fill with character 0. Note that the fill is matrix transformed like all other Mode 7 tiles. x/y = Horizontal/Veritcal mirroring. If the bit is set, flip the 256x256 pixel 'screen' in that direction. See the section "BACKGROUNDS" below for details. | Background Information |
$211B | 4 bytes | SNES Register (PPU) | ww+++- M7A - Mode 7 Matrix A (also used with $2134/6) ww+++- M7B - Mode 7 Matrix B (also used with $2134/6) ww+++- M7C - Mode 7 Matrix C ww+++- M7D - Mode 7 Matrix D aaaaaaaa aaaaaaaa Note that these are "write twice" registers, first the low byte is written then the high. Current theory is that writes to the register work like this: Reg = (Current<<8) | Prev; Prev = Current; Note that there is only one Prev shared by all these registers. This Prev is NOT shared with the BGnxOFS registers, but it IS shared with the M7xOFS registers. These set the matrix parameters for Mode 7. The values are an 8-bit fixed point, i.e. the value should be divided by 256.0 when used in calculations. See below for more explanation. The product A*(B>>8) may be read from registers $2134/6. There is supposedly no important delay. It may not be operative during Mode 7 rendering. See the section "BACKGROUNDS" below for details. | Background Information |
$211F | 2 bytes | SNES Register (PPU) | ww+++- M7X - Mode 7 Center X ww+++- M7Y - Mode 7 Center Y ---xxxxx xxxxxxxx Note that these are "write twice" registers, like the other M7* registers. See above for the write semantics. The value is 13 bit two's-complement signed. The matrix transformation formula is: [ X ] [ A B ] [ SX + M7HOFS - CX ] [ CX ] [ ] = [ ] * [ ] + [ ] [ Y ] [ C D ] [ SY + M7VOFS - CY ] [ CY ] Note: SX/SY are screen coordinates. X/Y are coordinates in the playing field from which the pixel is taken. If $211a bit 7 is clear, the result is then restricted to 0<=X<=1023 and 0<=Y<=1023. If $211a bits 6 and 7 are both set and X or Y is less than 0 or greater than 1023, use the low 3 bits of each to choose the pixel from character 0. The bit-accurate formula seems to be something along the lines of: #define CLIP(a) (((a)&0x2000)?((a)|~0x3ff):((a)&0x3ff)) X[0,y] = ((A*CLIP(HOFS-CX))&~63) + ((B*y)&~63) + ((B*CLIP(VOFS-CY))&~63) + (CX<<8) Y[0,y] = ((C*CLIP(HOFS-CX))&~63) + ((D*y)&~63) + ((D*CLIP(VOFS-CY))&~63) + (CY<<8) X[x,y] = X[x-1,y] + A Y[x,y] = Y[x-1,y] + C (In all cases, X[] and Y[] are fixed point with 8 bits of fraction) See the section "BACKGROUNDS" below for details. | Background Information |
$2121 | 1 byte | SNES Register (PPU) | wb+++- CGADD - CGRAM Address cccccccc This sets the word address (i.e. color) which will be affected by $2122 and $213b. | |
$2122 | 1 byte | SNES Register (PPU) | ww+++- CGDATA - CGRAM Data write -bbbbbgg gggrrrrr This writes to CGRAM, effectively setting the palette colors. Accesses to CGRAM are handled just like accesses to the low table of OAM, see $2104 for details. Note that the color values are stored in BGR order. | |
$2123 | 3 bytes | SNES Register (PPU) | wb+++- W12SEL - Window Mask Settings for BG1 and BG2 wb+++- W34SEL - Window Mask Settings for BG3 and BG4 wb+++- WOBJSEL - Window Mask Settings for OBJ and Color Window ABCDabcd c = Enable window 1 for BG1/BG3/OBJ a = Enable window 2 for BG1/BG3/OBJ C/A = Enable window 1/2 for BG2/BG4/Color When the bit is set, the corresponding window will affect the corresponding background (subject to the settings of $212e/f). d = Window 1 Inversion for BG1/BG3/OBJ b = Window 2 Inversion for BG1/BG3/OBJ D/B = Window 1/2 Inversion for BG2/BG4/Color When the bit is set, "W" should be replaced by "~W" (not-W) in the window combination formulae below. See the section "WINDOWS" below for more details. | Windowing Information |
$2126 | 4 bytes | SNES Register (PPU) | wb+++- WH0 - Window 1 Left Position wb+++- WH1 - Window 1 Right Position wb+++- WH2 - Window 2 Left Position wb+++- WH3 - Window 2 Right Position xxxxxxxx These set the offset of the appropriate edge of the appropriate window. Note that if the left edge is greater than the right edge, the window is considered to have no range at all (and thus "W" always is false). See the section "WINDOWS" below for more details. | Windowing Information |
$212A | 2 bytes | SNES Register (PPU) | wb+++- WBGLOG - Window mask logic for BGs 44332211 wb+++- WOBJLOG - Window mask logic for OBJs and Color Window ----ccoo 44/33/22/11/oo/cc = Mask logic for BG1/BG2/BG3/BG4/OBJ/Color This specified the window combination method, using standard boolean operators: 00 = OR 01 = AND 10 = XOR 11 = XNOR Consider two variables, W1 and W2, which are true for pixels between the appropriate left and right bounds as set in $2126-$2129 and false otherwise. Then, you have the following possibilities: (replace "W#" with "~W#", depending on the Inversion settings of $2123-$2125) Neither window enabled => nothing masked. One window enabled => Either W1 or W2, as appropriate. Both windows enabled => W1 op W2, where "op" is as above. Where the function is true, the BG will be masked. See the section "WINDOWS" below for more details. | Windowing Information |
$212C | 2 bytes | SNES Register (PPU) | wb+++- TM - Main Screen Designation wb+++- TS - Subscreen Designation ---o4321 1/2/3/4/o = Enable BG1/BG2/BG3/BG4/OBJ for display on the main (or sub) screen. See the section "BACKGROUNDS" below for details. | Background Information |
$212E | 2 bytes | SNES Register (PPU) | wb+++- TMW - Window Mask Designation for the Main Screen wb+++- TSW - Window Mask Designation for the Subscreen ---o4321 1/2/3/4/o = Enable window masking for BG1/BG2/BG3/BG4/OBJ on the main (or sub) screen. See the section "BACKGROUNDS" below for details. | Background Information |
$2130 | 1 byte | SNES Register (PPU) | wb+++- CGWSEL - Color Addition Select ccmm--sd cc = Clip colors to black before math 00 => Never 01 => Outside Color Window only 10 => Inside Color Window only 11 => Always mm = Prevent color math 00 => Never 01 => Outside Color Window only 10 => Inside Color Window only 11 => Always s = Add subscreen (instead of fixed color) d = Direct color mode for 256-color BGs See the sections "BACKGROUNDS", "WINDOWS", and "RENDERING THE SCREEN" below for details. | Background Information Windowing Information Rendering the Screen |
$2131 | 1 byte | SNES Register (PPU) | wb+++- CGADSUB - Color math designation shbo4321 s = Add/subtract select 0 => Add the colors 1 => Subtract the colors h = Half color math. When set, the result of the color math is divided by 2 (except when $2130 bit 1 is set and the fixed color is used, or when color is cliped). 4/3/2/1/o/b = Enable color math on BG1/BG2/BG3/BG4/OBJ/Backdrop See the sections "BACKGROUNDS", "WINDOWS", and "RENDERING THE SCREEN" below for details. | Background Information Windowing Information Rendering the Screen |
$2132 | 1 byte | SNES Register (PPU) | wb+++- COLDATA - Fixed Color Data bgrccccc b/g/r = Which color plane(s) to set the intensity for. ccccc = Color intensity. So basically, to set an orange you'd do something along the lines of: LDA #$3f STA $2132 LDA #$4f STA $2132 LDA #$80 STA $2132 See the sections "BACKGROUNDS" and "WINDOWS" below for details. | Background Information Windowing Information |
$2133 | 1 byte | SNES Register (PPU) | wb+++- SETINI - Screen Mode/Video Select se--poIi s = "External Sync". Used for superimposing "sfx" graphics, whatever that means. Usually 0. Not much is known about this bit. Interestingly, the SPPU chip has a pin named "EXTSYNC" (or not-EXTSYNC, since it has a bar over it) which is tied to Vcc. e = Mode 7 EXTBG ("Extra BG"). When this bit is set, you may enable BG2 on Mode 7. BG2 uses the same tile and character data as BG1, but interprets the high bit of the color data as a priority for the pixel. Various sources report additional effects for this bit, possibly related to bit 7. For example, "Enable the Data Supplied From the External Lsi.", whatever that means. Of course, maybe that's a typo and it's supposed to apply to bit 7 instead. p = Enable pseudo-hires mode. This creates a 512-pixel horizontal resolution by taking pixels from the subscreen for the even-numbered pixels (zero based) and from the main screen for the odd-numbered pixels. Color math behaves just as with Mode 5/6 hires. The interlace bit still has no effect. Mosaic operates as normal (not like Mode 5/6). The 'subscreen' pixel is clipped (by windows) when the main-screen pixel to the LEFT is clipped, not when the one to the RIGHT is clipped as you'd expect. What happens with pixel column 0 is unknown. Enabling this bit in Modes 5 or 6 has no effect. o = Overscan mode. When set, 239 lines will be displayed instead of the normal 224. This also means V-Blank will occur that much later, and be shorter. All that happens is that extra lines get added to the display, and it seems the TV will like to move the display up 8 pixels. See below for more details. I = OBJ Interlace. When set regardless of BG mode, the OBJ will be interlaced (see bit 0 below), and thus will appear half-height. Note that this only controls whether obj are drawn as normal or not; the interlace signal is only output to the TV based on bit 0 below. i = Screen interlace. When set in BG mode 5 (and probably 6), the effective screen height will be 448 (or 478) pixles, rather than 224 (or 239). When set in any other mode, the screen will just get a bit jumpy. However, toggling the tilemap each field would simulate the increased screen height (much like pseudo-hires simulares hires). In hardware, setting this bit makes the SNES output a normal interlace signal rather than always forcing one frame. See the sections "BACKGROUNDS" and "SPRITES" below for details. Overscan: The bit only matters at the very end of the frame, if you change the setting on line 0xE0 before the normal NMI trigger point then it's the same as if you had it on all frame. Note that this affects both the NMI trigger point and when HDMA stops for the frame. If you turn the bit off at the very beginning of scanline X (for 0xE1<=X<=0xF0), NMI will occur on line X and the last HDMA transfer will occur on line X-1. However, on my TV at least, the display will remain in the normal no-overscan position for lines E1-EC, it will move up only one pixel for line ED, and it will lose vertical sync for lines EF-F4! Turning the bit on, only line E1 gives any effect: NMI will occur on line E2, although the last HDMA will still occur on line E0. Anything else acts like you left the bit off the whole time. Note, however, that if you wait too long after the beginning of the scanline then you will get no effect. Even if there is no visible effect, the overscan setting still affects VRAM writes. In particular, executing "LDA #'-' / STA $2118 / LDA r2133 / STA $2133 / LDA #'+' / STA $2118" during the E1-F0 period will write only + or only - to VRAM, depending on whether the overscan bit was set to 0 or 1. | Background Information Sprite Information |
$2134 | 3 bytes | SNES Register (PPU) | r l+++? MPYL - Multiplication Result low byte r m+++? MPYM - Multiplication Result middle byte r h+++? MPYH - Multiplication Result high byte xxxxxxxx xxxxxxxx xxxxxxxx This is the 2's compliment product of the 16-bit value written to $211b and the 8-bit value most recently written to $211c. There is supposedly no important delay. It may not be operative during Mode 7 rendering. | |
$2137 | 1 byte | SNES Register (PPU) | b++++ SLHV - Software Latch for H/V Counter -------- When read, the H/V counter (as read from $213c and $213d) will be latched to the current X and Y position if bit 7 of $4201 is set. The data actually read is open bus. | |
$2138 | 1 byte | SNES Register (PPU) | r w++?- OAMDATAREAD* - Data for OAM read xxxxxxxx OAM reads are straightforward: the current byte as set in $2102/3 and incremented by reads from this register and writes to $2104 will be returned. Note that writes to the lower table are not affected so logically. See register $2104 and the section "SPRITES" below for details. Also, note that OAM address invalidation probably affects the address read by this register as well. | |
$2139 | 2 bytes | SNES Register (PPU) | r l++?- VMDATALREAD* - VRAM Data Read low byte r h++?- VMDATAHREAD* - VRAM Data Read high byte xxxxxxxx xxxxxxxx Simply, this reads data from VRAM. The address is incremented when either $2139 or $213a is read, depending on the setting of bit 7 of $2115. Actually, the reading is more complex. When either of these registers is read, the appropriate byte from a word-sized buffer is returned. A word from VRAM is loaded into this buffer just *before* the VRAM address is incremented. The actual data read and the amount of the increment depend on the low 4 bits of $2115. The effect of this is that a 'dummy read' is required after setting $2116-7 before you start getting the actual data. The interaction between these registers and $2118/9 is unknown. See the sections "BACKGROUNDS" and "SPRITES" below for details. | Background Information Sprite Information |
$213B | 1 byte | SNES Register (PPU) | r w++?- CGDATAREAD* - CGRAM Data read -bbbbbgg gggrrrrr This reads from CGRAM. Accesses to CGRAM are handled just like accesses to the low table of OAM, see $2138 for details. Note that the color values are stored in BGR order. The '-' bit is PPU2 Open Bus. | |
$213C | 2 bytes | SNES Register (PPU) | r w++++ OPHCT - Horizontal Scanline Location r w++++ OPVCT - Vertical Scanline Location -------x xxxxxxxx These values are latched by reading $2137 when bit 7 of $4201 is set, or by clearing-and-setting bit 7 of $4201 either by writing $4201 or by pin 6 of Controller Port 2 (the latch occurs on the 1->0 transition). Note that the value read is only 9 bits: bits 1-7 of the high byte are PPU2 Open Bus. Each register keeps seperate track of whether to return the low or high byte. The high/low selector is reset to 'low' when $213f is read (the selector is NOT reset when the counter is latched). H Counter values range from 0 to 339, with 22-277 being visible on the screen. V Counter values range from 0 to 261 in NTSC mode (262 is possible every other frame when interlace is active) and 0 to 311 in PAL mode (312 in interlace?), with 1-224 (or 1-239(?) if overscan is enabled) visible on the screen. | |
$213E | 1 byte | SNES Register (PPU) | r b++++ STAT77 - PPU Status Flag and Version trm-vvvv t = Time Over Flag. If more than 34 sprite-tiles (e.g. a 16x16 sprite has 2 sprite-tiles) were encountered on a single line, this flag will be set. The flag is reset at the end of V-Blank. See the section "SPRITES" below for details. r = Range Over Flag. If more than 32 sprites were encountered on a single line, this flag will be set. The flag is reset at the end of V-Blank. See the section "SPRITES" below for details. Note that the above two flags are set whether or not OBJ are actually enabled at the time. m = "Master/slave mode select". Little is known about this bit. Current theory is that it indicates the status of the "MASTER" pin on the S-PPU chip, which in the normal SNES is always Gnd. We always seem to read back 0 here. vvvv = 5c77 chip version number. So far, we've only encountered version 1. The '-' bit is PPU Open Bus. | Sprite Information |
$213F | 1 byte | SNES Register (PPU) | r b++++ STAT78 - PPU Status Flag and Version fl-pvvvv f = Interlace Field. This will toggle every V-Blank. l = External latch flag. When the PPU counters are latched, this flag gets set. The flag is reset on read, but only when $4201 bit 7 is set. p = NTSC/Pal Mode. If this is a PAL SNES, this bit will be set, otherwise it will be clear. vvvv = 5C78 chip version number. So far, we've encountered at least 2 and 3. Possibly 1 as well. The '-' bit is PPU2 Open Bus. Note: as a side effect of reading this register, the high/low byte selector for $213c/d is reset to 'low'. | |
$2140 | 4 bytes | SNES Register (APU) | rwb++++ APUIO0 - APU I/O register 0 rwb++++ APUIO1 - APU I/O register 1 rwb++++ APUIO2 - APU I/O register 2 rwb++++ APUIO3 - APU I/O register 3 xxxxxxxx These registers are used in communication with the SPC700. Note that the value written here is not the value read back. Rather, the value written shows up in the SPC700's registers $f4-7, and the values written to those registers by the SPC700 are what you read here. If the SPC700 writes the register during a read, the value read will be the logical OR of the old and new values. The exact cycles during which the 'read' actually occurs is not known, although a good guess would be some portion of the final 3 master cycles of the 6-cycle memory access. Note that these registers are mirrored throughout the range $2140-$217f. | |
$2180 | 1 byte | SNES Register (Hardware) | rwb++++ WMDATA - WRAM Data read/write xxxxxxxx This register reads to or writes from the WRAM address set in $2181-3. The address is then incremented. The effect of mixed reads and writes is unknown, but it is suspected that they are handled logically. Note that attempting a DMA from WRAM to this register will not work, WRAM will not be written. Attempting a DMA from this register to WRAM will similarly not work, the value written is (initially) the Open Bus value. In either case, the address in $2181-3 is not incremented. | |
$2181 | 3 bytes | SNES Register (Hardware) | wl++++ WMADDL - WRAM Address low byte wm++++ WMADDM - WRAM Address middle byte wh++++ WMADDH - WRAM Address high bit -------x xxxxxxxx xxxxxxxx This is the address that will be read or written by accesses to $2180. Note that WRAM is also mapped in the SNES memory space from $7E:0000 to $7F:FFFF, and from $0000 to $1FFF in banks $00 through $3F and $80 through $BF. Verious docs indicate that these registers may be read as well as written. However, they are wrong. These registers are open bus. DMA from WRAM to these registers has no effect. Otherwise, however, DMA writes them as normal. This means you could use DMA mode 4 to $2180 and a table in ROM to write any sequence of RAM addresses. The value does not wrap at page boundaries on increment. | |
$3000 | 2 bytes | Super FX Register | Default Source/Destination Register (R0) | |
$3002 | 2 bytes | Super FX Register | X coordinate for PLOT instruction (R1) | |
$3004 | 2 bytes | Super FX Register | Y coordinate for PLOT instruction (R2) | |
$3006 | 2 bytes | Super FX Register | General purpose register (R3) | |
$3008 | 2 bytes | Super FX Register | Lower 16 bits of result from LMULT instruction (R4) | |
$300A | 2 bytes | Super FX Register | General purpose register (R5) | |
$300C | 2 bytes | Super FX Register | Multiplier for FMULT and LMULT instructions (R6) | |
$300E | 2 bytes | Super FX Register | Source 1 (fixed point texel X position) for MERGE instruction (R7) | |
$3010 | 2 bytes | Super FX Register | Source 2 (fixed point texel Y position) for MERGE instruction (R8) | |
$3012 | 2 bytes | Super FX Register | General purpose register (R9) | |
$3014 | 2 bytes | Super FX Register | General purpose register, commonly used as stack pointer (R10) | |
$3016 | 2 bytes | Super FX Register | Destination for LINK instruction (R11) | |
$3018 | 2 bytes | Super FX Register | Counter for LOOP instruction (R12) | |
$301A | 2 bytes | Super FX Register | Branch for LOOP instruction (R13) | |
$301C | 2 bytes | Super FX Register | ROM Address Pointer for GETB, GETBH, GETBL, GETBS (R14) | |
$301E | 2 bytes | Super FX Register | Program Counter (R15) | |
$3030 | 2 bytes | Super FX Register | Status/Flag Register: Indicates the status of the Super FX. I--BHL21 -RGVNCZ- I = IRQ, set to 1 when Super FX caused an interrupt. Set to 0 when read by 65c816. B = Set to 1 when the WITH instruction is executed H = Immediate higher 8-bit flag L = Immediate lower 8-bit flag 2 = ALT2 mode set-up flag for the next instruction 1 = ALT1 mode set-up flag for the next instruction R = Set to 1 when reading ROM using R14 address G = Go flag, set to 1 when the Super FX is running V = Overflow flag N = Negative flag C = Carry flag Z = Zero flag | |
$3032 | 1 byte | Super FX Register | Unused. | |
$3033 | 1 byte | Super FX Register | Backup RAM Register: Makes sure the data at banks $78-$79 gets protected (or not) for writing, write-only. | |
$3034 | 1 byte | Super FX Register | Program Bank Register: Specifies the memory bank register to be accessed. Usually changed with the LJMP instruction. | |
$3035 | 1 byte | Super FX Register | Unused. | |
$3036 | 1 byte | Super FX Register | ROM Bank Register: When using the ROM buffering system, this register specifies the bank of the game pak ROM being copied into the buffer. The ROMB instruction is the general method used to change this register. | |
$3037 | 1 byte | Super FX Register | Control Flags Config Register: Selects the operating speed of the multiplier in the Super FX and sets up a mask for the interrupt signal, write-only. I-0----- I = IRQ, normal or masked 0 = MS, standard or high-speed. Should be set to 0 if the Super FX is running at 21 MHz (see $3039). | |
$3038 | 1 byte | Super FX Register | Screen Base Register: This register sets the starting address of the graphics storage area. It is written to directly, rather than through a specific instruction. | |
$3039 | 1 byte | Super FX Register | Clock Speed Register: This register assigns the Super FX operating frequency, write-only. 10.7 MHz or 21.4 MHz depending on bit 0. | |
$303A | 1 byte | Super FX Register | Screen Mode Register: Specifies the color gradient and screen height during PLOT processing and controls ROM and RAM bus assignments, write-only. --HRWhMm Hh = Screen Height 00 = 128 pixels 01 = 160 pixels 10 = 192 pixels 11 = OBJ Mode R = Game Pak ROM Access - RON 0 = SNES 1 = Super FX W = Game Pak Work RAM Access - RAN 0 = SNES 1 = Super FX Mm = Color Mode 00 = 4 colors 01 = 16 colors 10 = Not used 11 = 256 colors | |
$303B | 1 byte | Super FX Register | Version Code Register: Checks for the version of the Super FX chip, read-only. | |
$303C | 1 byte | Super FX Register | RAM Bank Register: When writing between the game WRAM and the Super FX registers, this register specifies the bank of the Game Pak RAM being used. The RAMB instruction is the general method used to change this register. Only one bit is used to set the RAM bank to $70 or $71. | |
$303D | 1 byte | Super FX Register | Unused. | |
$303E | 2 bytes | Super FX Register | Cache Base Register: This register specifies the address of either the Game Pak ROM or WRAM where data will be loaded from into the cache. Both the LJMP and CACHE instructions are accepted ways to change this register. | |
$3100 | 512 bytes | Super FX Register | Instruction cache, about 3 times faster than ROM and RAM. | |
$4016 | 2 bytes | SNES Register (Controller) | rwb++++ JOYSER0 - NES-style Joypad Access Port 1 Rd: ------ca Wr: -------l r?b++++ JOYSER1 - NES-style Joypad Access Port 2 ---111db These registers basically have a direct connection to the controller ports on the front of the SNES. l = Writing this bit controlls the Latch line of both controller ports. When 1 is set, the Latch goes high (or is it low? At any rate, whichever one makes the pads latch their state). When cleared, the Latch goes the other way. a/b = These bits return the state of the Data1 line. c/d = These bits return the state of the Data2 line. Reading $4016 drives the Clock line of Controller Port 1 low. The SNES then reads the Data1 and Data2 lines, and Clock is set back to high. $4017 does the same for Port 2. Note the 1-bits in $4017: the CPU chip has pins for these bits, but these pins are tied to Gnd and thus always 1. Data for normal joypads is returned in the order: B, Y, Select, Start, Up, Down, Left, Right, A, X, L, R, 0, 0, 0, 0, then ones until latched again. Note that Auto-Joypad Read (see register $4200) will effectively write 1 then 0 to bit 'l', then read 16 times from both $4016 and $4017. The 'a' bits will end up in $4218/9, with the first bit read (e.g. the B button) in bit 15 of the word. Similarly, the 'b' bits end up in $421a/b, the 'c' bits in $42c/d, and the 'd' bits in $421e/f. Any further bits the device may return may be read from $4016/$4017 as normal. The effect of reading these during auto-joypad read is unknown. See the section "CONTROLLERS" below for details. | Controller Information |
$4200 | 1 byte | SNES Register (Hardware) | wb+++? NMITIMEN - Interrupt Enable Flags n-yx---a n = Enable NMI. If clear, NMI will not occur. If set, NMI will fire just after the start of V-Blank. NMI fires shortly after the V Counter reaches $E1 (or presumably $F0 if overscan is enabled, see register $2133). x/y = IRQ enable. 0/0 = No IRQ will occur 0/1 = An IRQ will occur sometime just after the V Counter reaches the value set in $4209/$420A. 1/0 = An IRQ will occur sometime just after the H Counter reaches the value set in $4207/$4208. 1/1 = An IRQ will occur sometime just after the H Counter reaches the value set in $4207/$4208 when V Counter equals the value set in $4209/$420A. a = Auto-Joypad Read Enable. When set, the registers $4218-$421F will be updated at about V Counter = $E3 (or presumably $F2). Some games try to read this register. However, they work only because open bus behavior gives them values they expect. This register is initialized to $00 on power on or reset. | |
$4201 | 1 byte | SNES Register (Hardware) | wb++++ WRIO - Programmable I/O port (out-port) abxxxxxx This is basically just an 8-bit I/O Port. 'b' is connected to pin 6 of Controller Port 1. 'a' is connected to pin 6 of Controller Port 2, and to the PPU Latch line. Thus, writing a 0 then a 1 to bit 'a' will latch the H and V Counters much like reading $2137 (the latch happens on the transition to 0). When bit 'a' is 0, no latching can occur. Any other effects of this register are unknown. See $4213 for the I half of the I/O Port. Note that the IO Port is initialized as if this register were written with all 1-bits at power up, unchanged on reset(?). | |
$4202 | 2 bytes | SNES Register (Hardware) | wb++++ WRMPYA - Multiplicand A wb++++ WRMPYB - Multiplicand B mmmmmmmm Write $4202, then $4203. 8 "machine cycles" (probably 48 master cycles) after $4203 is set, the product may be read from $4216/7. $4202 will not be altered by this process, thus a new value may be written to $4203 to perform another multiplication without resetting $4202. The multiplication is unsigned. $4202 holds the value $ff on power on and is unchanged on reset. | |
$4204 | 3 bytes | SNES Register (Hardware) | wl++++ WRDIVL - Dividend C low byte wh++++ WRDIVH - Dividend C high byte dddddddd dddddddd wb++++ WRDIVB - Divisor B bbbbbbbb Write $4204/5, then $4206. 16 "machine cycles" (probably 96 master cycles) after $4206 is set, the quotient may be read from $4214/5, and the remainder from $4216/7. Presumably, $4204/5 are not altered by this process, much like $4202. The division is unsigned. Division by 0 gives a quotient of $FFFF and a remainder of C. WRDIV holds the value $ffff on power on and is unchanged on reset. | |
$4207 | 2 bytes | SNES Register (Hardware) | wl++++ HTIMEL - H Timer low byte wh++++ HTIMEH - H Timer high byte -------h hhhhhhhh If bit 4 of $4200 is set and bit 5 is clear, an IRQ will fire every scanline when the H Counter reaches the value set here. If bits 4 and 5 are both set, the IRQ will fire only when the V Counter equals the value set in $4209/a. Note that the H Counter ranges from 0 to 339, thus greater values will result in no IRQ firing. HTIME is initialized to $1ff on power on, unchanged on reset. | |
$4209 | 2 bytes | SNES Register (Hardware) | wl++++ VTIMEL - V Timer low byte wh++++ VTIMEH - V Timer high byte -------v vvvvvvvv If bit 5 of $4200 is set and bit 4 is clear, an IRQ will fire just after the V Counter reaches the value set here. If bits 4 and 5 are both set, the IRQ will fire instead when the V Counter equals the value set here and the H Counter reaches the value set in $4207/8. Note that the V Counter ranges from 0 to 261 in NTSC mode (262 is possible every other frame whan interlace is active) and 0 to 311 in PAL mode (312 in interlace?), thus greater values will result in no IRQ firing. VTIME is initialized to $1ff on power on, unchanged on reset. | |
$420B | 1 byte | SNES Register (DMA) | wb++++ MDMAEN - DMA Enable 76543210 7/6/5/4/3/2/1/0 = Enable the selected DMA channels. The CPU will be paused until all DMAs complete. DMAs will be executed in order from 0 to 7 (?). See registers $43x0-$43xA for more details. If HDMA (init or transfer) occurs while a DMA is in progress, the DMA will be paused for the duration. If the HDMA happens to involve the current DMA channel, the DMA will be immediately terminated and the HDMA will progress using the then-current values of the registers. Other DMA channels will be unaffected. This register is initialized to $00 on power on or reset. See the section "DMA AND HDMA" below for more information. | DMA and HDMA Information |
$420C | 1 byte | SNES Register (DMA) | wb++++ HDMAEN - HDMA Enable 76543210 7/6/5/4/3/2/1/0 = Enable the selected HDMA channels. HDMAs will be executed in order from 0 to 7 (?). See registers $43x0-$43xA for more details. If HDMA (init or transfer) occurs while a DMA is in progress, the DMA will be paused for the duration. If the HDMA happens to involve the current DMA channel, the DMA will be immediately terminated and the HDMA will progress using the then-current values of the registers. Other DMA channels will be unaffected. Note that enabling a channel mid-frame will begin HDMA at the next HDMA point. However, the HDMA register initialization only occurs before the HDMA point on scanline 0, so those registers will have to be initialized by hand before enabling HDMA. A channel that has already terminated for the frame cannot be restarted in this manner. Writing 0 to a bit will pause an ongoing HDMA; the transfer may be continued by writing 1 to the bit. This register is initialized to $00 on power on or reset. See the section "DMA AND HDMA" below for more information. | DMA and HDMA Information |
$420D | 1 byte | SNES Register (Hardware) | wb++++ MEMSEL - ROM Access Speed -------f f = FastROM select. The SNES uses a master clock running at about 21.477 MHz (current theory is 1.89e9/88 Hz). By default, the SNES takes 8 master cycles for each ROM access. If this bit is set and ROM is accessed via banks $80-$FF, only 6 master cycles will be used. This register is initialized to $00 on power on (or reset?). See my memory map and timing doc (memmap.txt) for more details. | Memory Map and Timings |
$4210 | 1 byte | SNES Register (Hardware) | r b++++ RDNMI - NMI Flag and 5A22 Version n---vvvv n = NMI Flag. This bit is set at the start of V-Blank (at the moment, we suspect when H-Counter is somewhere between $28 and $4E), and cleared on read or at the end of V-Blank. Supposedly, it is required that this register be read during NMI. Note that this bit is not affected by bit 7 of $4200. vvvv = 5A22 chip version number. So far, we've encountered at least 2, maybe 1 as well. NMI is cleared on power on or reset. The '-' bits are open bus. | |
$4211 | 1 byte | SNES Register (Hardware) | r b++++ TIMEUP - IRQ Flag i------- i = IRQ Flag. This bit is set just after an IRQ fires (at the moment, it seems to have the same delay as the NMI Flag of $4210 has following NMI), and is cleared on read or write. Supposedly, it is required that this register be read during the IRQ handler. If this really is the case, then I suspect that that read is what actually clears the CPU's IRQ line. This register is marked read/write in another doc, with no explanation. IRQ is cleared on power on or reset. The '-' bits are open bus. | |
$4212 | 1 byte | SNES Register (Hardware) | r b++++ HVBJOY - PPU Status vh-----a v = V-Blank Flag. If we're currently in V-Blank, this flag is set, otherwise it is clear. The setting seems to occur at H Counter about $16-$17 when V Counter is $E1, and the clearing at about $1E with V Counter 0. h = H-Blank Flag. If we're currently in H-Blank, this flag is set, otherwise it is clear. The setting seems to occur at H Counter about $121-$122, and the clearing at about $12-$18. a = Auto-Joypad Status. This is set while Auto-Joypad Read is in progress, and cleared when complete. It typically turns on at the start of V-Blank, and completes 3 scanlines later. This register is marked read/write in another doc, with no explanation. | |
$4213 | 1 byte | SNES Register (Hardware) | r b++++ RDIO - Programmable I/O port (in-port) abxxxxxx Reading this register reads data from the I/O Port. The way the I/O Port works, any bit set to 0 in $4201 will be 0 here. Any bit set to 1 in $4201 may be 1 or 0 here, depending on whether any other device connected to the I/O Port has set a 0 to that bit. Bit 'b' is connected to pin 6 of Controller Port 1. Bit 'a' is connected to pin 6 of Controller Port 2, and to the PPU Latch line. See register $4201 for the O side of the I/O Port. | |
$4214 | 2 bytes | SNES Register (Hardware) | r l++++ RDDIVL - Quotient of Divide Result low byte r h++++ RDDIVH - Quotient of Divide Result high byte qqqqqqqq qqqqqqqq Write $4204/5, then $4206. 16 "machine cycles" (probably 96 master cycles) after $4206 is set, the quotient may be read from these registers, and the remainder from $4216/7. The division is unsigned. | |
$4216 | 2 bytes | SNES Register (Hardware) | r l++++ RDMPYL - Multiplication Product or Divide Remainder low byte r h++++ RDMPYH - Multiplication Product or Divide Remainder high byte xxxxxxxx xxxxxxxx Write $4202, then $4203. 8 "machine cycles" (probably 48 master cycles) after $4203 is set, the product may be read from these registers. Write $4204/5, then $4206. 16 "machine cycles" (probably 96 master cycles) after $4206 is set, the quotient may be read from $4214/5, and the remainder from these registers. The multiplication and division are both unsigned. | |
$4218 | 8 bytes | SNES Register (Controller) | r l++++ JOY1L - Controller Port 1 Data1 Register low byte r h++++ JOY1H - Controller Port 1 Data1 Register high byte r l++++ JOY2L - Controller Port 2 Data1 Register low byte r h++++ JOY2H - Controller Port 2 Data1 Register high byte r l++++ JOY3L - Controller Port 1 Data2 Register low byte r h++++ JOY3H - Controller Port 1 Data2 Register high byte r l++++ JOY4L - Controller Port 2 Data2 Register low byte r h++++ JOY4H - Controller Port 2 Data2 Register high byte byetUDLR axlr0000 The bitmap above only applies for joypads, obviously. More generically, Auto Joypad Read effectively sets 1 then 0 to $4016, then reads $4016/7 16 times to get the bits for these registers. a/b/x/y/l/r/e/t = A/B/X/Y/L/R/Select/Start button status. U/D/L/R = Up/Down/Left/Right control pad status. Note that only one of L/R and only one of U/D may be set, due to the pad hardware. These registers are only updated when the Auto-Joypad Read bit (bit 0) of $4200 is set. They are being updated while the Auto-Joypad Status bit (bit 0) of $4212 is set. Reading during this time will return incorrect values. See the section "CONTROLLERS" below for details. | Controller Information |
$4300 | 1 byte | SNES Register (DMA) | rwb++++ DMAP0 - DMA Control for Channel 0 da-ifttt d = Transfer Direction. When clear, data will be read from the CPU memory and written to the PPU register. When set, vice versa. Contrary to previous belief, this bit DOES affect HDMA! Indirect mode is more useful, it will read the table as normal and write from Bus B to the Bus A address specified. Direct mode will work as expected though, it will read counts from the table and try to write the data values into the table. a = HDMA Addressing Mode. When clear, the HDMA table contains the data to transfer. When set, the HDMA table contains pointers to the data. This bit does not affect DMA. i = DMA Address Increment. When clear, the DMA address will be incremented for each byte. When set, the DMA address will be decremented. This bit does not affect HDMA. f = DMA Fixed Transfer. When set, the DMA address will not be adjusted. When clear, the address will be adjusted as specified by bit 4. This bit does not affect HDMA. ttt = Transfer Mode. 000 => 1 register write once (1 byte: p ) 001 => 2 registers write once (2 bytes: p, p+1 ) 010 => 1 register write twice (2 bytes: p, p ) 011 => 2 registers write twice each (4 bytes: p, p, p+1, p+1) 100 => 4 registers write once (4 bytes: p, p+1, p+2, p+3) 101 => 2 registers write twice alternate (4 bytes: p, p+1, p, p+1) 110 => 1 register write twice (2 bytes: p, p ) 111 => 2 registers write twice each (4 bytes: p, p, p+1, p+1) The effect of writing this register during HDMA to the associated channel is unknown. Most likely, the change takes effect for the next HDMA transfer. This register is set to $FF on power on, and is unchanged on reset. | |
$4301 | 1 byte | SNES Register (DMA) | rwb++++ BBAD0 - DMA Destination Register for Channel 0 pppppppp This specifies the Bus B address to access. Considering the standard CPU memory space, this specifies which address $00:2100-$00:21FF to access, with two- and four-register modes wrapping $21FF->$2100, not $2200. The effect of writing this register during HDMA to the associated channel is unknown. Most likely, the change takes effect for the next transfer. This register is set to $FF on power on, and is unchanged on reset. | |
$4302 | 3 bytes | SNES Register (DMA) | rwl++++ A1T0L - DMA Source Address for Channel 0 low byte rwh++++ A1T0H - DMA Source Address for Channel 0 high byte rwb++++ A1B0 - DMA Source Address for Channel 0 bank byte bbbbbbbb hhhhhhhh llllllll This specifies the starting Address Bus A address for the DMA transfer, or the beginning of the HDMA table for HDMA transfers. Note that Bus A does not access the Bus B registers, so pointing this address at say $00:2100 results in open bus. The effect of writing this register during HDMA to the associated channel is unknown. However, current theory is that only $4304 will affect the transfer. The changes will take effect at the next HDMA init. During DMA, $4302/3 will be incremented or decremented as specified by $4300. However $4304 will NOT be adjusted. These registers will not be affected by HDMA. This register is set to $FF on power on, and is unchanged on reset. | |
$4305 | 3 bytes | SNES Register (DMA) | rwl++++ DAS0L - DMA Size/HDMA Indirect Address low byte rwh++++ DAS0H - DMA Size/HDMA Indirect Address high byte rwb++++ DASB0 - HDMA Indirect Address bank byte bbbbbbbb hhhhhhhh llllllll For DMA, $4305/6 indicate the number of bytes to transfer. Note that this is a strict limit: if this is set to 1 then only 1 byte will be written, even if the transfer mode specifies 2 or 4 registers (and if this is 5, all 4 registers would be written once, then the first only would be written a second time). Note, however, that writing $0000 to this register actually results in a transfer of $10000 bytes, not 0. $4305/6 are decremented during DMA, and thus typically end up set to 0 when DMA is complete. For HDMA, $4307 specifies the bank for indirect addressing mode. The indirect address is copied into $4305/6 and incremented appropriately. For direct HDMA, these registers are not used or altered. Writes to $4307 during indirect HDMA will take effect for the next transfer. Writes to $4305/6 during indirect HDMA will also take effect for the next HDMA transfer, however this is only noticable during repeat mode (for normal mode, a new indirect address will be read from the table before the transfer). For a direct transfer, presumably nothing will happen. This register is set to $FF on power on, and is unchanged on reset. | |
$4308 | 2 bytes | SNES Register (DMA) | rwl++++ A2A0L - HDMA Table Address low byte rwh++++ A2A0H - HDMA Table Address high byte aaaaaaaa aaaaaaaa At the beginning of the frame $4302/3 are copied into this register for all active HDMA channels, and then this register is updated as the table is read. Thus, if a game wishes to start HDMA mid-frame (or change tables mid-frame), this register must be written. Writing this register mid-frame changes the table address for the next scanline. This register is not used for DMA. This register is set to $FF on power on, and is unchanged on reset. | |
$430A | 1 byte | SNES Register (DMA) | rwb++++ NLTR0 - HDMA Line Counter rccccccc r = Repeat Select. When set, the HDMA transfer will be performed every line, rather than only when this register is loaded from the table. However, this byte (and the indirect HDMA address) will only be reloaded from the table when the counter reaches 0. ccccccc = Line count. This is decremented every scanline. When it reaches 0, a byte is read from the HDMA table into this register (and the indirect HDMA address is read into $4305/6 if applicable). One oddity: the register is decremeted before being checked for r status or c==0. Thus, setting a value of $80 is really "128 lines with no repeat" rather than "0 lines with repeat". Similarly, a value of $00 will be "128 lines with repeat" when it doesn't mean "terminate the channel". This register is initialized at the end of V-Blank for every active HDMA channel. Note that if a game wishes to begin HDMA during the frame, it will most likely have to initalize this register. Writing this mid-transfer will similarly change the count and repeat to take effect next scanline. Remember though that 'repeat' won't take effect until after the next transfer period. This register is set to $ff on power on, and is unchanged on reset. See the section "DMA AND HDMA" below for more information. | DMA and HDMA Information |
$430B | 2 bytes | SNES Register (DMA) | rwb++++ ????0 - Unknown rwb++++ ????0 - Unknown ???????? The effects of these registers (if any) are unknown. $430F and $430B are really aliases for the same register. This register is set to $FF on power on, and is unchanged on reset. | |
$4310 | 1 byte | SNES Register (DMA) | rwb++++ DMAP1 - DMA Control for Channel 1 da-ifttt d = Transfer Direction. When clear, data will be read from the CPU memory and written to the PPU register. When set, vice versa. Contrary to previous belief, this bit DOES affect HDMA! Indirect mode is more useful, it will read the table as normal and write from Bus B to the Bus A address specified. Direct mode will work as expected though, it will read counts from the table and try to write the data values into the table. a = HDMA Addressing Mode. When clear, the HDMA table contains the data to transfer. When set, the HDMA table contains pointers to the data. This bit does not affect DMA. i = DMA Address Increment. When clear, the DMA address will be incremented for each byte. When set, the DMA address will be decremented. This bit does not affect HDMA. f = DMA Fixed Transfer. When set, the DMA address will not be adjusted. When clear, the address will be adjusted as specified by bit 4. This bit does not affect HDMA. ttt = Transfer Mode. 000 => 1 register write once (1 byte: p ) 001 => 2 registers write once (2 bytes: p, p+1 ) 010 => 1 register write twice (2 bytes: p, p ) 011 => 2 registers write twice each (4 bytes: p, p, p+1, p+1) 100 => 4 registers write once (4 bytes: p, p+1, p+2, p+3) 101 => 2 registers write twice alternate (4 bytes: p, p+1, p, p+1) 110 => 1 register write twice (2 bytes: p, p ) 111 => 2 registers write twice each (4 bytes: p, p, p+1, p+1) The effect of writing this register during HDMA to the associated channel is unknown. Most likely, the change takes effect for the next HDMA transfer. This register is set to $FF on power on, and is unchanged on reset. | |
$4311 | 1 byte | SNES Register (DMA) | rwb++++ BBAD1 - DMA Destination Register for Channel 1 pppppppp This specifies the Bus B address to access. Considering the standard CPU memory space, this specifies which address $00:2100-$00:21FF to access, with two- and four-register modes wrapping $21FF->$2100, not $2200. The effect of writing this register during HDMA to the associated channel is unknown. Most likely, the change takes effect for the next transfer. This register is set to $FF on power on, and is unchanged on reset. | |
$4312 | 3 bytes | SNES Register (DMA) | rwl++++ A1T1L - DMA Source Address for Channel 1 low byte rwh++++ A1T1H - DMA Source Address for Channel 1 high byte rwb++++ A1B1 - DMA Source Address for Channel 1 bank byte bbbbbbbb hhhhhhhh llllllll This specifies the starting Address Bus A address for the DMA transfer, or the beginning of the HDMA table for HDMA transfers. Note that Bus A does not access the Bus B registers, so pointing this address at say $00:2100 results in open bus. The effect of writing this register during HDMA to the associated channel is unknown. However, current theory is that only $4314 will affect the transfer. The changes will take effect at the next HDMA init. During DMA, $4312/3 will be incremented or decremented as specified by $4310. However $4314 will NOT be adjusted. These registers will not be affected by HDMA. This register is set to $FF on power on, and is unchanged on reset. | |
$4315 | 3 bytes | SNES Register (DMA) | rwl++++ DAS1L - DMA Size/HDMA Indirect Address low byte rwh++++ DAS1H - DMA Size/HDMA Indirect Address high byte rwb++++ DASB1 - HDMA Indirect Address bank byte bbbbbbbb hhhhhhhh llllllll For DMA, $4315/6 indicate the number of bytes to transfer. Note that this is a strict limit: if this is set to 1 then only 1 byte will be written, even if the transfer mode specifies 2 or 4 registers (and if this is 5, all 4 registers would be written once, then the first only would be written a second time). Note, however, that writing $0000 to this register actually results in a transfer of $10000 bytes, not 0. $4315/6 are decremented during DMA, and thus typically end up set to 0 when DMA is complete. For HDMA, $4317 specifies the bank for indirect addressing mode. The indirect address is copied into $4315/6 and incremented appropriately. For direct HDMA, these registers are not used or altered. Writes to $4317 during indirect HDMA will take effect for the next transfer. Writes to $4315/6 during indirect HDMA will also take effect for the next HDMA transfer, however this is only noticable during repeat mode (for normal mode, a new indirect address will be read from the table before the transfer). For a direct transfer, presumably nothing will happen. This register is set to $FF on power on, and is unchanged on reset. | |
$4318 | 2 bytes | SNES Register (DMA) | rwl++++ A2A1L - HDMA Table Address low byte rwh++++ A2A1H - HDMA Table Address high byte aaaaaaaa aaaaaaaa At the beginning of the frame $4312/3 are copied into this register for all active HDMA channels, and then this register is updated as the table is read. Thus, if a game wishes to start HDMA mid-frame (or change tables mid-frame), this register must be written. Writing this register mid-frame changes the table address for the next scanline. This register is not used for DMA. This register is set to $FF on power on, and is unchanged on reset. | |
$431A | 1 byte | SNES Register (DMA) | rwb++++ NLTR1 - HDMA Line Counter rccccccc r = Repeat Select. When set, the HDMA transfer will be performed every line, rather than only when this register is loaded from the table. However, this byte (and the indirect HDMA address) will only be reloaded from the table when the counter reaches 0. ccccccc = Line count. This is decremented every scanline. When it reaches 0, a byte is read from the HDMA table into this register (and the indirect HDMA address is read into $4315/6 if applicable). One oddity: the register is decremeted before being checked for r status or c==0. Thus, setting a value of $80 is really "128 lines with no repeat" rather than "0 lines with repeat". Similarly, a value of $00 will be "128 lines with repeat" when it doesn't mean "terminate the channel". This register is initialized at the end of V-Blank for every active HDMA channel. Note that if a game wishes to begin HDMA during the frame, it will most likely have to initalize this register. Writing this mid-transfer will similarly change the count and repeat to take effect next scanline. Remember though that 'repeat' won't take effect until after the next transfer period. This register is set to $ff on power on, and is unchanged on reset. See the section "DMA AND HDMA" below for more information. | DMA and HDMA Information |
$431B | 2 bytes | SNES Register (DMA) | rwb++++ ????1 - Unknown rwb++++ ????1 - Unknown ???????? The effects of these registers (if any) are unknown. $431F and $431B are really aliases for the same register. This register is set to $FF on power on, and is unchanged on reset. | |
$4320 | 1 byte | SNES Register (DMA) | rwb++++ DMAP2 - DMA Control for Channel 2 da-ifttt d = Transfer Direction. When clear, data will be read from the CPU memory and written to the PPU register. When set, vice versa. Contrary to previous belief, this bit DOES affect HDMA! Indirect mode is more useful, it will read the table as normal and write from Bus B to the Bus A address specified. Direct mode will work as expected though, it will read counts from the table and try to write the data values into the table. a = HDMA Addressing Mode. When clear, the HDMA table contains the data to transfer. When set, the HDMA table contains pointers to the data. This bit does not affect DMA. i = DMA Address Increment. When clear, the DMA address will be incremented for each byte. When set, the DMA address will be decremented. This bit does not affect HDMA. f = DMA Fixed Transfer. When set, the DMA address will not be adjusted. When clear, the address will be adjusted as specified by bit 4. This bit does not affect HDMA. ttt = Transfer Mode. 000 => 1 register write once (1 byte: p ) 001 => 2 registers write once (2 bytes: p, p+1 ) 010 => 1 register write twice (2 bytes: p, p ) 011 => 2 registers write twice each (4 bytes: p, p, p+1, p+1) 100 => 4 registers write once (4 bytes: p, p+1, p+2, p+3) 101 => 2 registers write twice alternate (4 bytes: p, p+1, p, p+1) 110 => 1 register write twice (2 bytes: p, p ) 111 => 2 registers write twice each (4 bytes: p, p, p+1, p+1) The effect of writing this register during HDMA to the associated channel is unknown. Most likely, the change takes effect for the next HDMA transfer. This register is set to $FF on power on, and is unchanged on reset. | |
$4321 | 1 byte | SNES Register (DMA) | rwb++++ BBAD2 - DMA Destination Register for Channel 2 pppppppp This specifies the Bus B address to access. Considering the standard CPU memory space, this specifies which address $00:2100-$00:21FF to access, with two- and four-register modes wrapping $21FF->$2100, not $2200. The effect of writing this register during HDMA to the associated channel is unknown. Most likely, the change takes effect for the next transfer. This register is set to $FF on power on, and is unchanged on reset. | |
$4322 | 3 bytes | SNES Register (DMA) | rwl++++ A1T2L - DMA Source Address for Channel 2 low byte rwh++++ A1T2H - DMA Source Address for Channel 2 high byte rwb++++ A1B2 - DMA Source Address for Channel 2 bank byte bbbbbbbb hhhhhhhh llllllll This specifies the starting Address Bus A address for the DMA transfer, or the beginning of the HDMA table for HDMA transfers. Note that Bus A does not access the Bus B registers, so pointing this address at say $00:2100 results in open bus. The effect of writing this register during HDMA to the associated channel is unknown. However, current theory is that only $4324 will affect the transfer. The changes will take effect at the next HDMA init. During DMA, $4322/3 will be incremented or decremented as specified by $4322/3. However $4324 will NOT be adjusted. These registers will not be affected by HDMA. This register is set to $FF on power on, and is unchanged on reset. | |
$4325 | 3 bytes | SNES Register (DMA) | rwl++++ DAS2L - DMA Size/HDMA Indirect Address low byte rwh++++ DAS2H - DMA Size/HDMA Indirect Address high byte rwb++++ DASB2 - HDMA Indirect Address bank byte bbbbbbbb hhhhhhhh llllllll For DMA, $4325/6 indicate the number of bytes to transfer. Note that this is a strict limit: if this is set to 1 then only 1 byte will be written, even if the transfer mode specifies 2 or 4 registers (and if this is 5, all 4 registers would be written once, then the first only would be written a second time). Note, however, that writing $0000 to this register actually results in a transfer of $10000 bytes, not 0. $4325/6 are decremented during DMA, and thus typically end up set to 0 when DMA is complete. For HDMA, $4327 specifies the bank for indirect addressing mode. The indirect address is copied into $4325/6 and incremented appropriately. For direct HDMA, these registers are not used or altered. Writes to $4327 during indirect HDMA will take effect for the next transfer. Writes to $4325/6 during indirect HDMA will also take effect for the next HDMA transfer, however this is only noticable during repeat mode (for normal mode, a new indirect address will be read from the table before the transfer). For a direct transfer, presumably nothing will happen. This register is set to $FF on power on, and is unchanged on reset. | |
$4328 | 2 bytes | SNES Register (DMA) | rwl++++ A2A2L - HDMA Table Address low byte rwh++++ A2A2H - HDMA Table Address high byte aaaaaaaa aaaaaaaa At the beginning of the frame $4322/3 are copied into this register for all active HDMA channels, and then this register is updated as the table is read. Thus, if a game wishes to start HDMA mid-frame (or change tables mid-frame), this register must be written. Writing this register mid-frame changes the table address for the next scanline. This register is not used for DMA. This register is set to $FF on power on, and is unchanged on reset. | |
$432A | 1 byte | SNES Register (DMA) | rwb++++ NLTR2 - HDMA Line Counter rccccccc r = Repeat Select. When set, the HDMA transfer will be performed every line, rather than only when this register is loaded from the table. However, this byte (and the indirect HDMA address) will only be reloaded from the table when the counter reaches 0. ccccccc = Line count. This is decremented every scanline. When it reaches 0, a byte is read from the HDMA table into this register (and the indirect HDMA address is read into $4325/6 if applicable). One oddity: the register is decremeted before being checked for r status or c==0. Thus, setting a value of $80 is really "128 lines with no repeat" rather than "0 lines with repeat". Similarly, a value of $00 will be "128 lines with repeat" when it doesn't mean "terminate the channel". This register is initialized at the end of V-Blank for every active HDMA channel. Note that if a game wishes to begin HDMA during the frame, it will most likely have to initalize this register. Writing this mid-transfer will similarly change the count and repeat to take effect next scanline. Remember though that 'repeat' won't take effect until after the next transfer period. This register is set to $ff on power on, and is unchanged on reset. See the section "DMA AND HDMA" below for more information. | DMA and HDMA Information |
$432B | 2 bytes | SNES Register (DMA) | rwb++++ ????2 - Unknown rwb++++ ????2 - Unknown ???????? The effects of these registers (if any) are unknown. $432F and $432B are really aliases for the same register. This register is set to $FF on power on, and is unchanged on reset. | |
$4330 | 1 byte | SNES Register (DMA) | rwb++++ DMAP3 - DMA Control for Channel 3 da-ifttt d = Transfer Direction. When clear, data will be read from the CPU memory and written to the PPU register. When set, vice versa. Contrary to previous belief, this bit DOES affect HDMA! Indirect mode is more useful, it will read the table as normal and write from Bus B to the Bus A address specified. Direct mode will work as expected though, it will read counts from the table and try to write the data values into the table. a = HDMA Addressing Mode. When clear, the HDMA table contains the data to transfer. When set, the HDMA table contains pointers to the data. This bit does not affect DMA. i = DMA Address Increment. When clear, the DMA address will be incremented for each byte. When set, the DMA address will be decremented. This bit does not affect HDMA. f = DMA Fixed Transfer. When set, the DMA address will not be adjusted. When clear, the address will be adjusted as specified by bit 4. This bit does not affect HDMA. ttt = Transfer Mode. 000 => 1 register write once (1 byte: p ) 001 => 2 registers write once (2 bytes: p, p+1 ) 010 => 1 register write twice (2 bytes: p, p ) 011 => 2 registers write twice each (4 bytes: p, p, p+1, p+1) 100 => 4 registers write once (4 bytes: p, p+1, p+2, p+3) 101 => 2 registers write twice alternate (4 bytes: p, p+1, p, p+1) 110 => 1 register write twice (2 bytes: p, p ) 111 => 2 registers write twice each (4 bytes: p, p, p+1, p+1) The effect of writing this register during HDMA to the associated channel is unknown. Most likely, the change takes effect for the next HDMA transfer. This register is set to $FF on power on, and is unchanged on reset. | |
$4331 | 1 byte | SNES Register (DMA) | rwb++++ BBAD3 - DMA Destination Register for Channel 3 pppppppp This specifies the Bus B address to access. Considering the standard CPU memory space, this specifies which address $00:2100-$00:21FF to access, with two- and four-register modes wrapping $21FF->$2100, not $2200. The effect of writing this register during HDMA to the associated channel is unknown. Most likely, the change takes effect for the next transfer. This register is set to $FF on power on, and is unchanged on reset. | |
$4332 | 3 bytes | SNES Register (DMA) | rwl++++ A1T3L - DMA Source Address for Channel 3 low byte rwh++++ A1T3H - DMA Source Address for Channel 3 high byte rwb++++ A1B3 - DMA Source Address for Channel 3 bank byte bbbbbbbb hhhhhhhh llllllll This specifies the starting Address Bus A address for the DMA transfer, or the beginning of the HDMA table for HDMA transfers. Note that Bus A does not access the Bus B registers, so pointing this address at say $00:2100 results in open bus. The effect of writing this register during HDMA to the associated channel is unknown. However, current theory is that only $4334 will affect the transfer. The changes will take effect at the next HDMA init. During DMA, $4332/3 will be incremented or decremented as specified by $4332/3. However $4334 will NOT be adjusted. These registers will not be affected by HDMA. This register is set to $FF on power on, and is unchanged on reset. | |
$4335 | 3 bytes | SNES Register (DMA) | rwl++++ DAS3L - DMA Size/HDMA Indirect Address low byte rwh++++ DAS3H - DMA Size/HDMA Indirect Address high byte rwb++++ DASB3 - HDMA Indirect Address bank byte bbbbbbbb hhhhhhhh llllllll For DMA, $4335/6 indicate the number of bytes to transfer. Note that this is a strict limit: if this is set to 1 then only 1 byte will be written, even if the transfer mode specifies 2 or 4 registers (and if this is 5, all 4 registers would be written once, then the first only would be written a second time). Note, however, that writing $0000 to this register actually results in a transfer of $10000 bytes, not 0. $4335/6 are decremented during DMA, and thus typically end up set to 0 when DMA is complete. For HDMA, $4337 specifies the bank for indirect addressing mode. The indirect address is copied into $4335/6 and incremented appropriately. For direct HDMA, these registers are not used or altered. Writes to $4337 during indirect HDMA will take effect for the next transfer. Writes to $4335/6 during indirect HDMA will also take effect for the next HDMA transfer, however this is only noticable during repeat mode (for normal mode, a new indirect address will be read from the table before the transfer). For a direct transfer, presumably nothing will happen. This register is set to $FF on power on, and is unchanged on reset. | |
$4338 | 2 bytes | SNES Register (DMA) | rwl++++ A2A3L - HDMA Table Address low byte rwh++++ A2A3H - HDMA Table Address high byte aaaaaaaa aaaaaaaa At the beginning of the frame $4332/3 are copied into this register for all active HDMA channels, and then this register is updated as the table is read. Thus, if a game wishes to start HDMA mid-frame (or change tables mid-frame), this register must be written. Writing this register mid-frame changes the table address for the next scanline. This register is not used for DMA. This register is set to $FF on power on, and is unchanged on reset. | |
$433A | 1 byte | SNES Register (DMA) | rwb++++ NLTR3 - HDMA Line Counter rccccccc r = Repeat Select. When set, the HDMA transfer will be performed every line, rather than only when this register is loaded from the table. However, this byte (and the indirect HDMA address) will only be reloaded from the table when the counter reaches 0. ccccccc = Line count. This is decremented every scanline. When it reaches 0, a byte is read from the HDMA table into this register (and the indirect HDMA address is read into $4335/6 if applicable). One oddity: the register is decremeted before being checked for r status or c==0. Thus, setting a value of $80 is really "128 lines with no repeat" rather than "0 lines with repeat". Similarly, a value of $00 will be "128 lines with repeat" when it doesn't mean "terminate the channel". This register is initialized at the end of V-Blank for every active HDMA channel. Note that if a game wishes to begin HDMA during the frame, it will most likely have to initalize this register. Writing this mid-transfer will similarly change the count and repeat to take effect next scanline. Remember though that 'repeat' won't take effect until after the next transfer period. This register is set to $ff on power on, and is unchanged on reset. See the section "DMA AND HDMA" below for more information. | DMA and HDMA Information |
$433B | 2 bytes | SNES Register (DMA) | rwb++++ ????3 - Unknown rwb++++ ????3 - Unknown ???????? The effects of these registers (if any) are unknown. $433F and $433B are really aliases for the same register. This register is set to $FF on power on, and is unchanged on reset. | |
$4340 | 1 byte | SNES Register (DMA) | rwb++++ DMAP4 - DMA Control for Channel 4 da-ifttt d = Transfer Direction. When clear, data will be read from the CPU memory and written to the PPU register. When set, vice versa. Contrary to previous belief, this bit DOES affect HDMA! Indirect mode is more useful, it will read the table as normal and write from Bus B to the Bus A address specified. Direct mode will work as expected though, it will read counts from the table and try to write the data values into the table. a = HDMA Addressing Mode. When clear, the HDMA table contains the data to transfer. When set, the HDMA table contains pointers to the data. This bit does not affect DMA. i = DMA Address Increment. When clear, the DMA address will be incremented for each byte. When set, the DMA address will be decremented. This bit does not affect HDMA. f = DMA Fixed Transfer. When set, the DMA address will not be adjusted. When clear, the address will be adjusted as specified by bit 4. This bit does not affect HDMA. ttt = Transfer Mode. 000 => 1 register write once (1 byte: p ) 001 => 2 registers write once (2 bytes: p, p+1 ) 010 => 1 register write twice (2 bytes: p, p ) 011 => 2 registers write twice each (4 bytes: p, p, p+1, p+1) 100 => 4 registers write once (4 bytes: p, p+1, p+2, p+3) 101 => 2 registers write twice alternate (4 bytes: p, p+1, p, p+1) 110 => 1 register write twice (2 bytes: p, p ) 111 => 2 registers write twice each (4 bytes: p, p, p+1, p+1) The effect of writing this register during HDMA to the associated channel is unknown. Most likely, the change takes effect for the next HDMA transfer. This register is set to $FF on power on, and is unchanged on reset. | |
$4341 | 1 byte | SNES Register (DMA) | rwb++++ BBAD4 - DMA Destination Register for Channel 4 pppppppp This specifies the Bus B address to access. Considering the standard CPU memory space, this specifies which address $00:2100-$00:21FF to access, with two- and four-register modes wrapping $21FF->$2100, not $2200. The effect of writing this register during HDMA to the associated channel is unknown. Most likely, the change takes effect for the next transfer. This register is set to $FF on power on, and is unchanged on reset. | |
$4342 | 3 bytes | SNES Register (DMA) | rwl++++ A1T4L - DMA Source Address for Channel 4 low byte rwh++++ A1T4H - DMA Source Address for Channel 4 high byte rwb++++ A1B4 - DMA Source Address for Channel 4 bank byte bbbbbbbb hhhhhhhh llllllll This specifies the starting Address Bus A address for the DMA transfer, or the beginning of the HDMA table for HDMA transfers. Note that Bus A does not access the Bus B registers, so pointing this address at say $00:2100 results in open bus. The effect of writing this register during HDMA to the associated channel is unknown. However, current theory is that only $4344 will affect the transfer. The changes will take effect at the next HDMA init. During DMA, $4342/3 will be incremented or decremented as specified by $4342/3. However $4344 will NOT be adjusted. These registers will not be affected by HDMA. This register is set to $FF on power on, and is unchanged on reset. | |
$4345 | 3 bytes | SNES Register (DMA) | rwl++++ DAS4L - DMA Size/HDMA Indirect Address low byte rwh++++ DAS4H - DMA Size/HDMA Indirect Address high byte rwb++++ DASB4 - HDMA Indirect Address bank byte bbbbbbbb hhhhhhhh llllllll For DMA, $4345/6 indicate the number of bytes to transfer. Note that this is a strict limit: if this is set to 1 then only 1 byte will be written, even if the transfer mode specifies 2 or 4 registers (and if this is 5, all 4 registers would be written once, then the first only would be written a second time). Note, however, that writing $0000 to this register actually results in a transfer of $10000 bytes, not 0. $4345/6 are decremented during DMA, and thus typically end up set to 0 when DMA is complete. For HDMA, $4347 specifies the bank for indirect addressing mode. The indirect address is copied into $4345/6 and incremented appropriately. For direct HDMA, these registers are not used or altered. Writes to $4347 during indirect HDMA will take effect for the next transfer. Writes to $4345/6 during indirect HDMA will also take effect for the next HDMA transfer, however this is only noticable during repeat mode (for normal mode, a new indirect address will be read from the table before the transfer). For a direct transfer, presumably nothing will happen. This register is set to $FF on power on, and is unchanged on reset. | |
$4348 | 2 bytes | SNES Register (DMA) | rwl++++ A2A4L - HDMA Table Address low byte rwh++++ A2A4H - HDMA Table Address high byte aaaaaaaa aaaaaaaa At the beginning of the frame $4342/3 are copied into this register for all active HDMA channels, and then this register is updated as the table is read. Thus, if a game wishes to start HDMA mid-frame (or change tables mid-frame), this register must be written. Writing this register mid-frame changes the table address for the next scanline. This register is not used for DMA. This register is set to $FF on power on, and is unchanged on reset. | |
$434A | 1 byte | SNES Register (DMA) | rwb++++ NLTR4 - HDMA Line Counter rccccccc r = Repeat Select. When set, the HDMA transfer will be performed every line, rather than only when this register is loaded from the table. However, this byte (and the indirect HDMA address) will only be reloaded from the table when the counter reaches 0. ccccccc = Line count. This is decremented every scanline. When it reaches 0, a byte is read from the HDMA table into this register (and the indirect HDMA address is read into $4345/6 if applicable). One oddity: the register is decremeted before being checked for r status or c==0. Thus, setting a value of $80 is really "128 lines with no repeat" rather than "0 lines with repeat". Similarly, a value of $00 will be "128 lines with repeat" when it doesn't mean "terminate the channel". This register is initialized at the end of V-Blank for every active HDMA channel. Note that if a game wishes to begin HDMA during the frame, it will most likely have to initalize this register. Writing this mid-transfer will similarly change the count and repeat to take effect next scanline. Remember though that 'repeat' won't take effect until after the next transfer period. This register is set to $ff on power on, and is unchanged on reset. See the section "DMA AND HDMA" below for more information. | DMA and HDMA Information |
$434B | 2 bytes | SNES Register (DMA) | rwb++++ ????4 - Unknown rwb++++ ????4 - Unknown ???????? The effects of these registers (if any) are unknown. $434F and $434B are really aliases for the same register. This register is set to $FF on power on, and is unchanged on reset. | |
$4350 | 1 byte | SNES Register (DMA) | rwb++++ DMAP5 - DMA Control for Channel 5 da-ifttt d = Transfer Direction. When clear, data will be read from the CPU memory and written to the PPU register. When set, vice versa. Contrary to previous belief, this bit DOES affect HDMA! Indirect mode is more useful, it will read the table as normal and write from Bus B to the Bus A address specified. Direct mode will work as expected though, it will read counts from the table and try to write the data values into the table. a = HDMA Addressing Mode. When clear, the HDMA table contains the data to transfer. When set, the HDMA table contains pointers to the data. This bit does not affect DMA. i = DMA Address Increment. When clear, the DMA address will be incremented for each byte. When set, the DMA address will be decremented. This bit does not affect HDMA. f = DMA Fixed Transfer. When set, the DMA address will not be adjusted. When clear, the address will be adjusted as specified by bit 4. This bit does not affect HDMA. ttt = Transfer Mode. 000 => 1 register write once (1 byte: p ) 001 => 2 registers write once (2 bytes: p, p+1 ) 010 => 1 register write twice (2 bytes: p, p ) 011 => 2 registers write twice each (4 bytes: p, p, p+1, p+1) 100 => 4 registers write once (4 bytes: p, p+1, p+2, p+3) 101 => 2 registers write twice alternate (4 bytes: p, p+1, p, p+1) 110 => 1 register write twice (2 bytes: p, p ) 111 => 2 registers write twice each (4 bytes: p, p, p+1, p+1) The effect of writing this register during HDMA to the associated channel is unknown. Most likely, the change takes effect for the next HDMA transfer. This register is set to $FF on power on, and is unchanged on reset. | |
$4351 | 1 byte | SNES Register (DMA) | rwb++++ BBAD5 - DMA Destination Register for Channel 5 pppppppp This specifies the Bus B address to access. Considering the standard CPU memory space, this specifies which address $00:2100-$00:21FF to access, with two- and four-register modes wrapping $21FF->$2100, not $2200. The effect of writing this register during HDMA to the associated channel is unknown. Most likely, the change takes effect for the next transfer. This register is set to $FF on power on, and is unchanged on reset. | |
$4352 | 3 bytes | SNES Register (DMA) | rwl++++ A1T5L - DMA Source Address for Channel 5 low byte rwh++++ A1T5H - DMA Source Address for Channel 5 high byte rwb++++ A1B5 - DMA Source Address for Channel 5 bank byte bbbbbbbb hhhhhhhh llllllll This specifies the starting Address Bus A address for the DMA transfer, or the beginning of the HDMA table for HDMA transfers. Note that Bus A does not access the Bus B registers, so pointing this address at say $00:2100 results in open bus. The effect of writing this register during HDMA to the associated channel is unknown. However, current theory is that only $4354 will affect the transfer. The changes will take effect at the next HDMA init. During DMA, $4352/3 will be incremented or decremented as specified by $4352/3. However $4354 will NOT be adjusted. These registers will not be affected by HDMA. This register is set to $FF on power on, and is unchanged on reset. | |
$4355 | 3 bytes | SNES Register (DMA) | rwl++++ DAS5L - DMA Size/HDMA Indirect Address low byte rwh++++ DAS5H - DMA Size/HDMA Indirect Address high byte rwb++++ DASB5 - HDMA Indirect Address bank byte bbbbbbbb hhhhhhhh llllllll For DMA, $4355/6 indicate the number of bytes to transfer. Note that this is a strict limit: if this is set to 1 then only 1 byte will be written, even if the transfer mode specifies 2 or 4 registers (and if this is 5, all 4 registers would be written once, then the first only would be written a second time). Note, however, that writing $0000 to this register actually results in a transfer of $10000 bytes, not 0. $4355/6 are decremented during DMA, and thus typically end up set to 0 when DMA is complete. For HDMA, $4357 specifies the bank for indirect addressing mode. The indirect address is copied into $4355/6 and incremented appropriately. For direct HDMA, these registers are not used or altered. Writes to $4357 during indirect HDMA will take effect for the next transfer. Writes to $4355/6 during indirect HDMA will also take effect for the next HDMA transfer, however this is only noticable during repeat mode (for normal mode, a new indirect address will be read from the table before the transfer). For a direct transfer, presumably nothing will happen. This register is set to $FF on power on, and is unchanged on reset. | |
$4358 | 2 bytes | SNES Register (DMA) | rwl++++ A2A5L - HDMA Table Address low byte rwh++++ A2A5H - HDMA Table Address high byte aaaaaaaa aaaaaaaa At the beginning of the frame $4352/3 are copied into this register for all active HDMA channels, and then this register is updated as the table is read. Thus, if a game wishes to start HDMA mid-frame (or change tables mid-frame), this register must be written. Writing this register mid-frame changes the table address for the next scanline. This register is not used for DMA. This register is set to $FF on power on, and is unchanged on reset. | |
$435A | 1 byte | SNES Register (DMA) | rwb++++ NLTR5 - HDMA Line Counter rccccccc r = Repeat Select. When set, the HDMA transfer will be performed every line, rather than only when this register is loaded from the table. However, this byte (and the indirect HDMA address) will only be reloaded from the table when the counter reaches 0. ccccccc = Line count. This is decremented every scanline. When it reaches 0, a byte is read from the HDMA table into this register (and the indirect HDMA address is read into $4355/6 if applicable). One oddity: the register is decremeted before being checked for r status or c==0. Thus, setting a value of $80 is really "128 lines with no repeat" rather than "0 lines with repeat". Similarly, a value of $00 will be "128 lines with repeat" when it doesn't mean "terminate the channel". This register is initialized at the end of V-Blank for every active HDMA channel. Note that if a game wishes to begin HDMA during the frame, it will most likely have to initalize this register. Writing this mid-transfer will similarly change the count and repeat to take effect next scanline. Remember though that 'repeat' won't take effect until after the next transfer period. This register is set to $ff on power on, and is unchanged on reset. See the section "DMA AND HDMA" below for more information. | DMA and HDMA Information |
$435B | 2 bytes | SNES Register (DMA) | rwb++++ ????5 - Unknown rwb++++ ????5 - Unknown ???????? The effects of these registers (if any) are unknown. $435F and $435B are really aliases for the same register. This register is set to $FF on power on, and is unchanged on reset. | |
$4360 | 1 byte | SNES Register (DMA) | rwb++++ DMAP6 - DMA Control for Channel 6 da-ifttt d = Transfer Direction. When clear, data will be read from the CPU memory and written to the PPU register. When set, vice versa. Contrary to previous belief, this bit DOES affect HDMA! Indirect mode is more useful, it will read the table as normal and write from Bus B to the Bus A address specified. Direct mode will work as expected though, it will read counts from the table and try to write the data values into the table. a = HDMA Addressing Mode. When clear, the HDMA table contains the data to transfer. When set, the HDMA table contains pointers to the data. This bit does not affect DMA. i = DMA Address Increment. When clear, the DMA address will be incremented for each byte. When set, the DMA address will be decremented. This bit does not affect HDMA. f = DMA Fixed Transfer. When set, the DMA address will not be adjusted. When clear, the address will be adjusted as specified by bit 4. This bit does not affect HDMA. ttt = Transfer Mode. 000 => 1 register write once (1 byte: p ) 001 => 2 registers write once (2 bytes: p, p+1 ) 010 => 1 register write twice (2 bytes: p, p ) 011 => 2 registers write twice each (4 bytes: p, p, p+1, p+1) 100 => 4 registers write once (4 bytes: p, p+1, p+2, p+3) 101 => 2 registers write twice alternate (4 bytes: p, p+1, p, p+1) 110 => 1 register write twice (2 bytes: p, p ) 111 => 2 registers write twice each (4 bytes: p, p, p+1, p+1) The effect of writing this register during HDMA to the associated channel is unknown. Most likely, the change takes effect for the next HDMA transfer. This register is set to $FF on power on, and is unchanged on reset. | |
$4361 | 1 byte | SNES Register (DMA) | rwb++++ BBAD6 - DMA Destination Register for Channel 6 pppppppp This specifies the Bus B address to access. Considering the standard CPU memory space, this specifies which address $00:2100-$00:21FF to access, with two- and four-register modes wrapping $21FF->$2100, not $2200. The effect of writing this register during HDMA to the associated channel is unknown. Most likely, the change takes effect for the next transfer. This register is set to $FF on power on, and is unchanged on reset. | |
$4362 | 3 bytes | SNES Register (DMA) | rwl++++ A1T6L - DMA Source Address for Channel 6 low byte rwh++++ A1T6H - DMA Source Address for Channel 6 high byte rwb++++ A1B6 - DMA Source Address for Channel 6 bank byte bbbbbbbb hhhhhhhh llllllll This specifies the starting Address Bus A address for the DMA transfer, or the beginning of the HDMA table for HDMA transfers. Note that Bus A does not access the Bus B registers, so pointing this address at say $00:2100 results in open bus. The effect of writing this register during HDMA to the associated channel is unknown. However, current theory is that only $4364 will affect the transfer. The changes will take effect at the next HDMA init. During DMA, $4362/3 will be incremented or decremented as specified by $4362/3. However $4364 will NOT be adjusted. These registers will not be affected by HDMA. This register is set to $FF on power on, and is unchanged on reset. | |
$4365 | 3 bytes | SNES Register (DMA) | rwl++++ DAS6L - DMA Size/HDMA Indirect Address low byte rwh++++ DAS6H - DMA Size/HDMA Indirect Address high byte rwb++++ DASB6 - HDMA Indirect Address bank byte bbbbbbbb hhhhhhhh llllllll For DMA, $4365/6 indicate the number of bytes to transfer. Note that this is a strict limit: if this is set to 1 then only 1 byte will be written, even if the transfer mode specifies 2 or 4 registers (and if this is 5, all 4 registers would be written once, then the first only would be written a second time). Note, however, that writing $0000 to this register actually results in a transfer of $10000 bytes, not 0. $4365/6 are decremented during DMA, and thus typically end up set to 0 when DMA is complete. For HDMA, $4367 specifies the bank for indirect addressing mode. The indirect address is copied into $4365/6 and incremented appropriately. For direct HDMA, these registers are not used or altered. Writes to $4367 during indirect HDMA will take effect for the next transfer. Writes to $4365/6 during indirect HDMA will also take effect for the next HDMA transfer, however this is only noticable during repeat mode (for normal mode, a new indirect address will be read from the table before the transfer). For a direct transfer, presumably nothing will happen. This register is set to $FF on power on, and is unchanged on reset. | |
$4368 | 2 bytes | SNES Register (DMA) | rwl++++ A2A6L - HDMA Table Address low byte rwh++++ A2A6H - HDMA Table Address high byte aaaaaaaa aaaaaaaa At the beginning of the frame $4362/3 are copied into this register for all active HDMA channels, and then this register is updated as the table is read. Thus, if a game wishes to start HDMA mid-frame (or change tables mid-frame), this register must be written. Writing this register mid-frame changes the table address for the next scanline. This register is not used for DMA. This register is set to $FF on power on, and is unchanged on reset. | |
$436A | 1 byte | SNES Register (DMA) | rwb++++ NLTR6 - HDMA Line Counter rccccccc r = Repeat Select. When set, the HDMA transfer will be performed every line, rather than only when this register is loaded from the table. However, this byte (and the indirect HDMA address) will only be reloaded from the table when the counter reaches 0. ccccccc = Line count. This is decremented every scanline. When it reaches 0, a byte is read from the HDMA table into this register (and the indirect HDMA address is read into $4365/6 if applicable). One oddity: the register is decremeted before being checked for r status or c==0. Thus, setting a value of $80 is really "128 lines with no repeat" rather than "0 lines with repeat". Similarly, a value of $00 will be "128 lines with repeat" when it doesn't mean "terminate the channel". This register is initialized at the end of V-Blank for every active HDMA channel. Note that if a game wishes to begin HDMA during the frame, it will most likely have to initalize this register. Writing this mid-transfer will similarly change the count and repeat to take effect next scanline. Remember though that 'repeat' won't take effect until after the next transfer period. This register is set to $ff on power on, and is unchanged on reset. See the section "DMA AND HDMA" below for more information. | DMA and HDMA Information |
$436B | 2 bytes | SNES Register (DMA) | rwb++++ ????6 - Unknown rwb++++ ????6 - Unknown ???????? The effects of these registers (if any) are unknown. $436F and $436B are really aliases for the same register. This register is set to $FF on power on, and is unchanged on reset. | |
$4370 | 1 byte | SNES Register (DMA) | rwb++++ DMAP7 - DMA Control for Channel 7 da-ifttt d = Transfer Direction. When clear, data will be read from the CPU memory and written to the PPU register. When set, vice versa. Contrary to previous belief, this bit DOES affect HDMA! Indirect mode is more useful, it will read the table as normal and write from Bus B to the Bus A address specified. Direct mode will work as expected though, it will read counts from the table and try to write the data values into the table. a = HDMA Addressing Mode. When clear, the HDMA table contains the data to transfer. When set, the HDMA table contains pointers to the data. This bit does not affect DMA. i = DMA Address Increment. When clear, the DMA address will be incremented for each byte. When set, the DMA address will be decremented. This bit does not affect HDMA. f = DMA Fixed Transfer. When set, the DMA address will not be adjusted. When clear, the address will be adjusted as specified by bit 4. This bit does not affect HDMA. ttt = Transfer Mode. 000 => 1 register write once (1 byte: p ) 001 => 2 registers write once (2 bytes: p, p+1 ) 010 => 1 register write twice (2 bytes: p, p ) 011 => 2 registers write twice each (4 bytes: p, p, p+1, p+1) 100 => 4 registers write once (4 bytes: p, p+1, p+2, p+3) 101 => 2 registers write twice alternate (4 bytes: p, p+1, p, p+1) 110 => 1 register write twice (2 bytes: p, p ) 111 => 2 registers write twice each (4 bytes: p, p, p+1, p+1) The effect of writing this register during HDMA to the associated channel is unknown. Most likely, the change takes effect for the next HDMA transfer. This register is set to $FF on power on, and is unchanged on reset. | |
$4371 | 1 byte | SNES Register (DMA) | rwb++++ BBAD7 - DMA Destination Register for Channel 7 pppppppp This specifies the Bus B address to access. Considering the standard CPU memory space, this specifies which address $00:2100-$00:21FF to access, with two- and four-register modes wrapping $21FF->$2100, not $2200. The effect of writing this register during HDMA to the associated channel is unknown. Most likely, the change takes effect for the next transfer. This register is set to $FF on power on, and is unchanged on reset. | |
$4372 | 3 bytes | SNES Register (DMA) | rwl++++ A1T7L - DMA Source Address for Channel 7 low byte rwh++++ A1T7H - DMA Source Address for Channel 7 high byte rwb++++ A1B7 - DMA Source Address for Channel 7 bank byte bbbbbbbb hhhhhhhh llllllll This specifies the starting Address Bus A address for the DMA transfer, or the beginning of the HDMA table for HDMA transfers. Note that Bus A does not access the Bus B registers, so pointing this address at say $00:2100 results in open bus. The effect of writing this register during HDMA to the associated channel is unknown. However, current theory is that only $4374 will affect the transfer. The changes will take effect at the next HDMA init. During DMA, $4372/3 will be incremented or decremented as specified by $4372/3. However $4374 will NOT be adjusted. These registers will not be affected by HDMA. This register is set to $FF on power on, and is unchanged on reset. | |
$4375 | 3 bytes | SNES Register (DMA) | rwl++++ DAS7L - DMA Size/HDMA Indirect Address low byte rwh++++ DAS7H - DMA Size/HDMA Indirect Address high byte rwb++++ DASB7 - HDMA Indirect Address bank byte bbbbbbbb hhhhhhhh llllllll For DMA, $4375/6 indicate the number of bytes to transfer. Note that this is a strict limit: if this is set to 1 then only 1 byte will be written, even if the transfer mode specifies 2 or 4 registers (and if this is 5, all 4 registers would be written once, then the first only would be written a second time). Note, however, that writing $0000 to this register actually results in a transfer of $10000 bytes, not 0. $4375/6 are decremented during DMA, and thus typically end up set to 0 when DMA is complete. For HDMA, $4377 specifies the bank for indirect addressing mode. The indirect address is copied into $4375/6 and incremented appropriately. For direct HDMA, these registers are not used or altered. Writes to $4377 during indirect HDMA will take effect for the next transfer. Writes to $4375/6 during indirect HDMA will also take effect for the next HDMA transfer, however this is only noticable during repeat mode (for normal mode, a new indirect address will be read from the table before the transfer). For a direct transfer, presumably nothing will happen. This register is set to $FF on power on, and is unchanged on reset. | |
$4378 | 2 bytes | SNES Register (DMA) | rwl++++ A2A7L - HDMA Table Address low byte rwh++++ A2A7H - HDMA Table Address high byte aaaaaaaa aaaaaaaa At the beginning of the frame $4372/3 are copied into this register for all active HDMA channels, and then this register is updated as the table is read. Thus, if a game wishes to start HDMA mid-frame (or change tables mid-frame), this register must be written. Writing this register mid-frame changes the table address for the next scanline. This register is not used for DMA. This register is set to $FF on power on, and is unchanged on reset. | |
$437A | 1 byte | SNES Register (DMA) | rwb++++ NLTR7 - HDMA Line Counter rccccccc r = Repeat Select. When set, the HDMA transfer will be performed every line, rather than only when this register is loaded from the table. However, this byte (and the indirect HDMA address) will only be reloaded from the table when the counter reaches 0. ccccccc = Line count. This is decremented every scanline. When it reaches 0, a byte is read from the HDMA table into this register (and the indirect HDMA address is read into $4375/6 if applicable). One oddity: the register is decremeted before being checked for r status or c==0. Thus, setting a value of $80 is really "128 lines with no repeat" rather than "0 lines with repeat". Similarly, a value of $00 will be "128 lines with repeat" when it doesn't mean "terminate the channel". This register is initialized at the end of V-Blank for every active HDMA channel. Note that if a game wishes to begin HDMA during the frame, it will most likely have to initalize this register. Writing this mid-transfer will similarly change the count and repeat to take effect next scanline. Remember though that 'repeat' won't take effect until after the next transfer period. This register is set to $ff on power on, and is unchanged on reset. See the section "DMA AND HDMA" below for more information. | DMA and HDMA Information |
$437B | 2 bytes | SNES Register (DMA) | rwb++++ ????7 - Unknown rwb++++ ????7 - Unknown ???????? The effects of these registers (if any) are unknown. $437F and $437B are really aliases for the same register. This register is set to $FF on power on, and is unchanged on reset. | |
Tweaks Address | Length | Type | Description | Details |
$0080F7 | 1 byte | Debug | Change from [38] to [00] to enable debug routine at $0080F8. | |
$00810D | 1 byte | Debug | [20] Number of frames to skip running gamemode code after initally pressing R when frame advance flag is set. | |
$00812C | 1 byte | Debug | [04] Number of frames to skip running game mode code between each frame where game mode is running when L or R is held on Controller 2 and frame advance flag is set. | |
$00853D | 1 byte | Music | Change to [04] to make music header setting E play the "Welcome to Yoshi's Island" music. To be used with $01B259. | |
$0086D8 | 1 byte | Boss | Change to [9C] to remove the ending Key Scene from Naval Piranha boss, when using the "OH MY!" trick. Default [A3]. | |
$018F0D | 1 byte | Boss | Hookbill the Koopa's HP, multiplied by 2. Default is [06]: 3 HP. | |
$018F31 | 2 bytes | Sound Effect | Sound that Hookbill the Koopa makes when you pound his stomach. Default is [80 00]. For a list of sounds, see here. | |
$018FB1 | 2 bytes | Sound Effect | Sound that Hookbill the Koopa makes when he coughs. Default is [39 00]. For a list of sounds, see here. | |
$019078 | 2 bytes | Sprite Number | Sprite that Hookbill will cough up when stomped off. Default is [25 00]: Sprite 25, Green Egg. NOTE: Not every sprite will spawn / work correctly. |
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$019118 | 2 bytes | Sound Effect | Sound that Hookbill the Koopa makes when he gets hit with an egg while crawling. Default is [3F 00]. For a list of sounds, see here. | |
$019210 | 2 bytes | Sound Effect | Sound that Hookbill the Koopa makes when he gets hit with an egg that knocks him over. Default is [3F 00]. For a list of sounds, see here. | |
$01A00B | 1 byte | Boss | Change to [9C] to remove the ending Key Scene from Hookbill the Koopa boss, after defeat. Default [A6]. | |
$01B259 | 1 byte | Music | Change to [02] to make music header setting E play the "Welcome to Yoshi's Island" music. To be used with $00853D. | |
$01B7D7 | 136 bytes | Misc. Tilemap | Table for the text shown in the Pause/Results screens: $01B7D7 - "HIGH SCORE" text line in the Results Screen: 22 bytes long (2 less than the others because this line has a one-tile border in each side). The first, second, twenty-first and twenty-second tiles will be overwriten with the Sun animation, while the eighteenth and nineteenth tiles will be overwriten depending on the player's total score. Default [3A 3C 4E 0E 10 0C 0E 4E 24 04 1C 22 08 36 36 36 36 54 5C 4E 3A 3C]. $01B7ED - "STARS" text line: 24 bytes long. The fourteenth, fifteenth, twenty-first, twenty-second and the bottom half of the twenty-fourth tiles will be overwritten depending on the player's star count. Default [3E 40 4E 24 26 00 22 24 36 36 36 36 36 36 50 34 56 50 68 6A 4E 50 6C 6E]. $01B805 - "COINS" text line: 24 bytes long. The fourteenth, fifteenth, twenty-first, twenty-second and the bottom half of the twenty-fourth tiles will be overwritten depending on the player's red coin count. Default [46 48 4E 04 1C 10 1A 24 36 36 36 36 36 36 50 34 54 50 68 6A 4E 50 6C 6E]. $01B81D - "FLOWERS" text line: 24 bytes long. The sixteenth, twenty-first and the bottom half of the twenty-fourth tiles will be overwritten depending on the player's flower count. Default [42 44 4E 0A 16 1C 2C 08 22 24 36 36 36 36 36 50 34 5A 68 6A 4E 50 6C 6E]. $01B835 - "TOTAL POINTS" text line: 21 bytes long (because it has 3 empty tiles on the left). The twenty-first, twenty-second and the bottom half of the twenty-fourth tiles will be overwritten depending on the player's total score. Default [26 1C 26 00 16 4E 1E 1C 10 1A 26 24 36 36 36 36 36 36 50 6C 6E]. $01B84A - "HIGH SCORE" text line in the Pause Screen: 21 bytes long (because it has 3 empty tiles on the left). The twenty-first, twenty-second and the bottom half of the twenty-fourth tiles will be overwritten depending on the player's total score. Default [4E 0E 10 0C 0E 4E 24 04 1C 22 08 36 36 36 36 36 36 36 50 6C 6E]. |
Input Basic Example |
$01BF2C | 12 bytes | Table | The bonus games which can be selected upon beating a stage in each world. These values correspond to the different bonus games: [00] - Flip Cards [02] - Scratch & Match [04] - Drawing Lots [06] - Match Cards [08] - Roulette [0A] - Slot Machine The default values are as follows: [00 02] - World 1 [04 0A] - World 2 [06 08] - World 3 [04 02] - World 4 [00 08] - World 5 [06 0A] - World 6 |
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$01C288 | 1 byte | Text | Change to 00 to disable the message that pops up when you lose Baby Mario for the first time. Default [04]. To be used with $01C28B. | |
$01C28B | 1 byte | Text | Change to 80 to disable the message that pops up when you lose Baby Mario for the first time. Default [D0]. To be used with $01C288. | |
$01DE94 | 1 byte | Sound Effect | Sound that message boxes makes when they appear (after the block is hit). Default is [50]. For a list of sounds, see here. | |
$0285D4 | 1 byte | Boss | Change to [9C] to remove the ending Key Scene from Roger the Potted Ghost boss, after defeat. Default [A3]. | |
$02941F | 1 byte | Text | Change to 80 to disable the tutorial message that pops up when you pass the first Middle Ring in the game. Default [D0]. | |
$02A7DC | 1 byte | Level Number | Stage Level number of the level where you never obtain a bonus challenge on the goal roulette (originally Extra 1 [08]) | |
$02B4E0 | 2 bytes | Sprite Number | Change what the Grinder (spits seeds of watermelon) spits (sprite 1A6). Default is [07 01]: Sprite 107, Seed of watermelon. NOTE: Not every sprite will spawn / work correctly. |
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$02B9C4 | 2 bytes | Sprite Number | Change what the Short Fuse throws (sprite 1A7 on Y=0). Default is [60 00]: Sprite 60, Bomb. NOTE: Not every sprite will spawn / work correctly. |
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$02B9C9 | 2 bytes | Sprite Number | Change what the Seedy Sally throws (sprite 1A7 on Y=1). Default is [F9 00]: Sprite F9, Yellow Needlenose (although in this specific case the Needlenose will be green). NOTE: Not every sprite will spawn / work correctly. |
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$02BCB3 | 2 bytes | Sprite Number | Change what the Grinder (climbing, spits seeds of watermelon) spits (sprite 1A9). Default is [07 01]: Sprite 107, Seed of watermelon. NOTE: Not every sprite will spawn / work correctly. |
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$02D770 | 1 byte | Boss | Change to [A3] to add the ending Key Scene to Sluggy the Unshaven boss, after defeat. Default [9C]. | |
$02E064 | 2 bytes | Boss | Change to [EA EA] to make all bosses have a ending Key Scene after defeated (originally only for X-8 bosses). Note that, this is the only way to have Marching Milde and Prince Froggy to have a proper Key Scene, since the individual setting doesn't work with them (with Froggy the scene become a softlock and with Marching Milde the key doesn't appear at all). Default [F0 27]. Keep in mind that X-4 bosses have a shorter ending scene, so the scene will be cut before the big keyhole appears. Also note that Prince Froggy's scene has graphical glitches for some reason. |
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$02E4B5 | 2 bytes | Boss | Naval Piranha's HP. Default is [03 00]. | |
$02F1F9 | 1 byte | Boss | Change to [9C] to remove the ending Key Scene from Naval Piranha boss, after defeat. Default [A6]. Note: Triggering the "OH MY!" trick will still show the Key Scene as usual. Check $0086D8 if you want to disable the scene in this case too. |
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$039BA1 | 2 bytes | ASM | Change from [F0 03] (BEQ #$03) to [80 00] (BRA #$00) to force bubbles to always give you one shot, or to [80 03] (BRA #$03) to force bubbles to always give you three shots. | |
$039BAD | 1 byte | Timer | The length of the pause when Yoshi eats a watermelon. Change to 00 to disable the pause when Yoshi eats a watermelon. Default [10]. | |
$03A527 | 2 bytes | Misc. | Coins required to get a life. Default is [64 00] (100 on hex) | |
$04BB7C | 1 byte | Boss | Change to [A3] to add the ending Key Scene to Bigger Boo boss, after defeat. Default [9C]. | |
$04E1AE | 1 byte | Misc. | Change to 1F to disable the Welcome level and immediately start at 1-1. Default [0B]. To be used with $04E1B4. | |
$04E1B4 | 1 byte | Misc. | Change to 00 to disable the Welcome level and immediately start at 1-1. Default [0B]. To be used with $04E1AE. | |
$05A087 | 1 byte | Boss | Change to [6B] to make Naval Piranha's small form immune to eggs (preventing the "OH, MY!" trick). Default [B9]. | |
$068CB5 | 1 byte | Boss | Change to [9C] to remove the ending Key Scene from Salvo the Slime boss, after defeat. Default [A3]. | |
$06A2E8 | 1 byte | Boss | Change to [A3] to add the ending Key Scene to Burt the Bashful boss, after defeat. Default [9C]. | |
$06E1F8 | 7 bytes | Sprite Physics | Change to [EA EA EA EA EA EA EA] to make the large sewer ghost spawn infinite Shy Guys (up to sprite limits), instead of stopping when you have full eggs. Default [A9 D5 91 22 44 DE 7E]. | |
$0781B8 | 2 bytes | Sprite Physics | Change what the Egg Plant shoots (sprite F4 on X=0) when shooting at normal speed. The values should be the same as the ones in $078250, in order to prevent unintended bugs or crashes. Default is [25 00]: Sprite 25, Green Egg. | How does the second byte works. |
$078250 | 2 bytes | Sprite Physics | Change what the Egg Plant shoots (sprite F4 on X=0) when shooting at fast speed (when Yoshi does a Ground Pound near them). The values should be the same as the ones in $0781B8, in order to prevent unintended bugs or crashes. Default is [25 00]: Sprite 25, Green Egg. | How does the second byte works. |
$0782F9 | 2 bytes | Sprite Physics | Change what the Needlenose Plant shoots (sprite F4 on X=1) when shooting at normal speed. The values should be the same as the ones in $078347, in order to prevent unintended bugs or crashes. Default is [63 01]: Sprite 163, Bouncing green Needlenose. | How does the second byte works. |
$078347 | 2 bytes | Sprite Physics | Change what the Needlenose Plant shoots (sprite F4 on X=1) when shooting at fast speed (when Yoshi does a Ground Pound near them). The values should be the same as the ones in $0782F9, in order to prevent unintended bugs or crashes. Default is [63 01]: Sprite 163, Bouncing green Needlenose. | How does the second byte works. |
$0ADA27 | 1 byte | Sprite Physics | Amount of times an egg will ricochet. Default value is [63] (corresponds to the Super FX comamnd sub #3). Change the "3" to change the number of bounces. |
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$0CE569 | 36 bytes | Sprite Palette | Boss palette pointers after transformation (3 bytes each): [CA A5 5F] - 1-4 Burt the Bashful [22 21 70] - 1-8 Salvo the Slime [22 21 70] - 2-4 Bigger Boo [22 21 70] - 2-8 Roger the Potted Ghost [A2 21 70] - 3-4 Prince Froggy [22 21 70] - 3-8 Naval Piranha [06 A6 5F] - 4-4 Marching Milde [22 21 70] - 4-8 Hookbill the Koopa [82 21 70] - 5-4 Sluggy the Unshaven [8E A5 5F] - 5-8 Raphael the Raven [42 A6 5F] - 6-4 Tap-Tap the Red Nose [C2 21 70] - 6-8 King Bowser If you change the bosses' location, you need to edit the pointers to fit your levels. |
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$0CE58D | 36 bytes | Sprite Palette | Boss palette pointers before transformation (3 bytes each): [02 21 70] - 1-4 Burt the Bashful [22 21 70] - 1-8 Salvo the Slime [82 21 70] - 2-4 Bigger Boo [22 21 70] - 2-8 Roger the Potted Ghost [22 21 70] - 3-4 Prince Froggy [22 21 70] - 3-8 Naval Piranha [A2 21 70] - 4-4 Marching Milde [22 21 70] - 4-8 Hookbill the Koopa [82 21 70] - 5-4 Sluggy the Unshaven [42 21 70] - 5-8 Raphael the Raven [42 21 70] - 6-4 Tap-Tap the Red Nose [02 21 70] - 6-8 King Bowser If you change the bosses' location, you need to edit the pointers to fit your levels. (Warning: For some reason, changing the pre-transformed palette pointers for X-4 bosses will result in them using the wrong palette... however, if you leave the pointer unchanged, the boss will appear fine) |
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$0DCB11 | 1 byte | Boss | Baby Bowser's HP (before transformation). If you change this, you need to put the same value minus one at $0DF133 (for the "defeat" sound effect). Default [03]. | |
$0DD940 | 1 byte | Boss | Giant Baby Bowser's HP. This value should be the same as $0DD980. Default is [07]. | |
$0DD980 | 1 byte | Boss | Giant Baby Bowser's HP. This value should be the same as $0DD940. Default is [07]. | |
$0DF133 | 1 byte | Boss | Baby Bowser's HP (before transformation) minus one. This is used to play the "defeat" sound at the correct hit. Default [02]. | |
$0EB534 | 1 byte | Text | Change to 80 to disable the tutorial message that pops up when you get your first flower in the game. Default [D0]. | |
$0EBEA1 | 1 byte | Sprite Palette | Item Memory index at which Chomp Rock in 1-1 will use the special palette. Default [01]. | |
$0EBEA7 | 1 byte | Sprite Palette | Translevel number of the level which will always use the special palette for Chomp Rock. Default is [28]: 4-5. | |
$0EBEC3 | 1 byte | Sprite Palette | Color of the special Chomp Rock. Default is [08]. [00] or [01] - Orange [02] or [03] - Green [04] or [05] - Gray (Default sprite palette) [06] or [07] - Light Blue (without black outline) [08] or [09] - Brown (Default special palette) Other values are still usable but gives bugged palettes. Values [0C], [0D], [0E], and [0F] depends on the Sprite Palette header, so they could or couldn't work. |
Palette Comparison |
$0F8EA6 | 8 bytes | Sprite Number | Which sprite (should be a winged cloud) the hidden winged ?-cloud (sprite $0067) turns into when touched by a chomp rock or snowball, depending on the initial X position. By default: $00C1 (5 stars), $00C8 (seed of sunflower), $00B8 (flower), $00B7 (1-up). | |
$0F8ED4 | 8 bytes | Subroutine | Whether the hidden ?-cloud reveiled by a chomp rock (sprite $0067) is affected by item memory or not depending on its content. Should be either $8EDC (affected by item memory) or $8EE8 (respawns every time). By default: $8EDC (5 stars), $8EE8 (seed of sunflower), $8EDC (flower), $8EDC (1-up). | |
$0F9C4D | 1 byte | Boss | The first of the four pointers of Tap-Tap the Red Nose boss battle. Change to the current translevel number, in the case you relocated the boss. Default is [3F]: 6-4. Use with 0F9CCF, 0F9DF2, and 0FA00D. | |
$0F9CCF | 1 byte | Boss | The second of the four pointers of Tap-Tap the Red Nose boss battle. Change to the current translevel number, in the case you relocated the boss. Default is [3F]: 6-4. Use with 0F9C4D, 0F9DF2, and 0FA00D. | |
$0F9DF2 | 1 byte | Boss | The third of the four pointers of Tap-Tap the Red Nose boss battle. Change to the current translevel number, in the case you relocated the boss. Default is [3F]: 6-4. Use with 0F9C4D, 0F9CCF, and 0FA00D. | |
$0FA00D | 1 byte | Boss | The fourth of the four pointers of Tap-Tap the Red Nose boss battle. Change to the current translevel number, in the case you relocated the boss. Default is [3F]: 6-4. Use with 0F9C4D, 0F9CCF, and 0F9DF2. | |
$0FA5B6 | 1 byte | Boss | Change to [A3] to add the ending Key Scene to Tap-Tap the Red Nose boss, after defeat. Default [9C]. | |
$0FB108 | 1 byte | Boss | Raphael the Raven's HP in unary, converted to hex. Default is [07]: 3 HP (111 in unary). Possible values: [01] - 1 HP [03] - 2 HP [07] - 3 HP [0F] - 4 HP [1F] - 5 HP [3F] - 6 HP [7F] - 7 HP [FF] - 8 HP If you change this, you should also change the byte at $0FB50D. |
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$0FB482 | 1 byte | Boss | Raphael the Raven's initial image. See $0FB6A1 for more information. Default [06]. | |
$0FB50D | 1 byte | Boss | Raphael the Raven's HP. This value should be the same as $0FB108. Default [07]. | |
$0FB6A1 | 8 bytes | Boss | Raphael the Raven's images after every hit, depending on its HP. Possible values: [00] - Whitish Body [01] - The same color as the sky (no outline) [02] - The same color as the sky with a star in its body (no outline) [05] - The same color as the sky with a star in its body (light blue outline) [06] - Normal [07] - Yellow Body (no outline) [08] - Angry [09] - Furious Any other values gives a wrong palette. The first byte of the table seems to be unused, being the byte at $0FB482 used for the initial image. Default values are [06 08 09 09 09 09 09 09]: Normal -> Angry -> Furious. |
Image Comparison |
$0FB72D | 1 byte | Boss | Change to [9C] to remove the ending Key Scene from Raphael the Raven boss, after defeat. Default [A6]. | |
$0FBCCB | 3 bytes | Cutscene | Change to [00 00 00] to disable the story cutscene before title screen. Default [15 02 46]. To be used with $0FBDFB and $0FBED1. | |
$0FBDFB | 3 bytes | Cutscene | Change to [EA EA EA] to disable the story cutscene before title screen. Default [8D 4D 00]. To be used with $0FBCCB and $0FBED1. | |
$0FBED1 | 2 bytes | Cutscene | Change to [F0 00] to disable the story cutscene before title screen. Default [F0 12]. To be used with $0FBCCB and $0FBDFB. | |
$10804E | 1 byte | Pause Screen | Change this from [80] to [00] to disable Start+Selecting out of the welcome level (requires each save file to be reloaded from the ROM to take effect). | |
$1080A6 | 1 byte | Misc. | Change this from [00] to [02] to make "Hasty" the default control scheme. (Requires reloading each save file from the ROM to take effect) | |
$10897F | 1 byte | Sound Effect | Sound that plays when "Nintendo Presents" shows. Default is [09]. For a list of sounds, see here. | |
$108D90 | 1 byte | Level Number | Translevel number of the first of three levels where Yoshi starts out facing left. Default is [04]: 1-5. | |
$108D94 | 1 byte | Level Number | Translevel number of the second of three levels where Yoshi starts out facing left. Default is [12]: 2-7. | |
$108D98 | 1 byte | Level Number | Translevel number of the third of three levels where Yoshi starts out facing left. Default is [36]: 5-7. | |
$108D9C | 1 byte | Misc. | Change to [00] to prevent Yoshi to face left in the selected levels (which are 1-5, 2-7 and 5-7 by default). Default is [02]. | |
$108DA2 | 1 byte | Text | Change to 80 to disable the intro stage's Welcome message. Default [D0]. | |
$10CDE6 | 1 byte | Misc. | The score threshold to generate the 3-Kamek variant of the "Drawing Lots" bonus game. Default is [32] which is 50 points. Setting this to [00] will force the 3-Kamek variant, while setting it to [65] or higher will force the 1-Kamek variant. |
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$10E189 | 1 byte | Misc. | The number of lives Yoshi starts with after continuing from the Game Over screen. Default is [03]. | |
$179933 | 1 byte | Misc. | The number of lives Yoshi starts with after selecting a save file. Default is [03]. | |
$179954 | 1 byte | Cutscene | Change to [1E] to disable both the intro scene and welcome level, and start directly on the map when starting a new game. Default is [37]. | |
$17A82E | 1 byte | Map | Change to [2E] to fix a bug where Green Yoshi's position shifts on the World 1 and World 3 maps, when exiting from the Extra level. Default [23]. | |
$3FA064 | 4 bytes | Sprite Palette | Change to [B5 24 55 3D] to fix Pink Yoshi's palette in game. This will do Mario's hat and Yoshi's tongue have the correct shading. Default [55 3D B5 24]. | Comparison Before and After |
$3FA0D8 | 2 bytes | Sprite Palette | Change to [00 00] to make Brown Yoshi in game uses the same palette it uses in the intro cutscene. Use with $3FA0DE and $3FA0E6. Default [6F 1D]. | |
$3FA0DE | 2 bytes | Sprite Palette | Change to [A9 0C] to make Brown Yoshi in game uses the same palette it uses in the intro cutscene. Use with $3FA0D8 and $3FA0E6. Default [F5 29]. | |
$3FA0E6 | 2 bytes | Sprite Palette | Change to [70 15] to make Brown Yoshi in game uses the same palette it uses in the intro cutscene. Use with $3FA0D8 and $3FA0DE. Default [BA 4A]. | |
$3FC876 | 2 bytes | Object Palette | Palette color of World Map 1 (hud) and File Select Menu, written backwards. Default is [FC 53] (SNES Color $53FC). | |
$3FC894 | 2 bytes | Object Palette | Palette color of World Map 2 (hud) and Copy File Menu, written backwards. Default is [B4 7B] (SNES Color $7BB4). | |
$3FC8B2 | 2 bytes | Object Palette | Palette color of World Map 3 (hud) and Erase File Menu, written backwards. Default is [3F 73] (SNES Color $733F). | |
$3FDAF8 | 2 bytes | Object Palette | Palette color of World Map 4 (hud) while being in World 1 (dynamic palette), written backwards. Default is [1B 73] (SNES Color $731B). | |
$3FDB16 | 2 bytes | Object Palette | Palette color of World Map 5 (hud) while being in World 1 (dynamic palette), written backwards. Default is [37 77] (SNES Color $7737). | |
$3FDB34 | 2 bytes | Object Palette | Palette color of World Map 6 (hud) while being in World 1 (dynamic palette), written backwards. Default is [DD 5A] (SNES Color $5ADD). | |
$3FDB74 | 2 bytes | Object Palette | Palette color of World Map 4 (hud) while being in World 2 (dynamic palette), written backwards. Default is [1B 73] (SNES Color $731B). | |
$3FDB92 | 2 bytes | Object Palette | Palette color of World Map 5 (hud) while being in World 2 (dynamic palette), written backwards. Default is [37 77] (SNES Color $7737). | |
$3FDBB0 | 2 bytes | Object Palette | Palette color of World Map 6 (hud) while being in World 2 (dynamic palette), written backwards. Default is [DD 5A] (SNES Color $5ADD). | |
$3FDBF0 | 2 bytes | Object Palette | Palette color of World Map 4 (hud) while being in World 3 (dynamic palette), written backwards. Default is [1B 73] (SNES Color $731B). | |
$3FDC0E | 2 bytes | Object Palette | Palette color of World Map 5 (hud) while being in World 3 (dynamic palette), written backwards. Default is [37 77] (SNES Color $7737). | |
$3FDC2C | 2 bytes | Object Palette | Palette color of World Map 6 (hud) while being in World 3 (dynamic palette), written backwards. Default is [DD 5A] (SNES Color $5ADD). | |
$3FDC6C | 2 bytes | Object Palette | Palette color of World Map 4 (hud) while being in World 4 (dynamic palette), written backwards. Default is [1B 73] (SNES Color $731B). | |
$3FDC8A | 2 bytes | Object Palette | Palette color of World Map 5 (hud) while being in World 4 (dynamic palette), written backwards. Default is [37 77] (SNES Color $7737). | |
$3FDCA8 | 2 bytes | Object Palette | Palette color of World Map 6 (hud) while being in World 4 (dynamic palette), written backwards. Default is [DD 5A] (SNES Color $5ADD). | |
$3FDCE8 | 2 bytes | Object Palette | Palette color of World Map 4 (hud) while being in World 5 (dynamic palette), written backwards. Default is [1B 73] (SNES Color $731B). | |
$3FDD06 | 2 bytes | Object Palette | Palette color of World Map 5 (hud) while being in World 5 (dynamic palette), written backwards. Default is [37 77] (SNES Color $7737). | |
$3FDD24 | 2 bytes | Object Palette | Palette color of World Map 6 (hud) while being in World 5 (dynamic palette), written backwards. Default is [DD 5A] (SNES Color $5ADD). | |
$3FDD64 | 2 bytes | Object Palette | Palette color of World Map 4 (hud) while being in World 6 (dynamic palette), written backwards. Default is [1B 73] (SNES Color $731B). | |
$3FDD82 | 2 bytes | Object Palette | Palette color of World Map 5 (hud) while being in World 6 (dynamic palette), written backwards. Default is [37 77] (SNES Color $7737). | |
$3FDDA0 | 2 bytes | Object Palette | Palette color of World Map 6 (hud) while being in World 6 (dynamic palette), written backwards. Default is [DD 5A] (SNES Color $5ADD). | |
$3FED72 | 4 bytes | Sprite Palette | Change to [B5 24 55 3D] to fix Pink Yoshi's palette in the intro cutscene. Used to complement $3FA064's fix (for the sake of color consistency). Default [55 3D B5 24]. | |