Inspired by FL4SHK I made my own CPU, except whereas his takes inspiration from the Gameboy's CPU, mine takes inspiration from the 6502.
His is too big to fit into the PowerPak's FPGA, but I explicitly kept mine small enough to fit, with the goal of using it as a coprocessor for NES demos.
While a lot of things take one more cycle than the 6502 does, I currently have it running at 21Mhz and it should be able to run at 42Mhz if I can figure out how to use the FPGA's clock doubler. The main obstacle that restricts its usefulness is the fact that the PowerPak's FPGA only has 3KB of block RAM, and block RAM is the only storage I could have used for the program. 3KB is still useful, though. In the context of the PowerPak I do currently have a problem where sometimes writes fail to happen, and I think I have some timing issues that I don't know how to resolve yet.
It's MIT licensed, and uses very few resources, so it should be easy to incorporate into any FPGA project that needs a small processor.
Instruction set. As you can see, the main difference my CPU has is the ability to leave out the parameter, where it's assumed to be zero. ADD and SUB also exist.
Diagram of the state machine
CPU test running on my NES
GitHub repository
nesdev thread
His is too big to fit into the PowerPak's FPGA, but I explicitly kept mine small enough to fit, with the goal of using it as a coprocessor for NES demos.
While a lot of things take one more cycle than the 6502 does, I currently have it running at 21Mhz and it should be able to run at 42Mhz if I can figure out how to use the FPGA's clock doubler. The main obstacle that restricts its usefulness is the fact that the PowerPak's FPGA only has 3KB of block RAM, and block RAM is the only storage I could have used for the program. 3KB is still useful, though. In the context of the PowerPak I do currently have a problem where sometimes writes fail to happen, and I think I have some timing issues that I don't know how to resolve yet.
It's MIT licensed, and uses very few resources, so it should be easy to incorporate into any FPGA project that needs a small processor.
Instruction set. As you can see, the main difference my CPU has is the ability to leave out the parameter, where it's assumed to be zero. ADD and SUB also exist.
Diagram of the state machine
CPU test running on my NES
GitHub repository
nesdev thread